590 lines
23 KiB
C
590 lines
23 KiB
C
/* $NetBSD: siopreg.h,v 1.10 1999/03/26 22:50:26 mhitch Exp $ */
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/*
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* Copyright (c) 1990 The Regents of the University of California.
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* All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* Van Jacobson of Lawrence Berkeley Laboratory.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)siopreg.h 7.3 (Berkeley) 2/5/91
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*/
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/*
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* NCR 53C710 SCSI interface hardware description.
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*
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* From the Mach scsi driver for the 53C700
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*/
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typedef struct {
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#ifndef ARCH_720
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/*00*/ volatile unsigned char siop_sien; /* rw: SCSI Interrupt Enable */
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/*01*/ volatile unsigned char siop_sdid; /* rw: SCSI Destination ID */
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/*02*/ volatile unsigned char siop_scntl1; /* rw: SCSI control reg 1 */
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/*03*/ volatile unsigned char siop_scntl0; /* rw: SCSI control reg 0 */
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/*04*/ volatile unsigned char siop_socl; /* rw: SCSI Output Control Latch */
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/*05*/ volatile unsigned char siop_sodl; /* rw: SCSI Output Data Latch */
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/*06*/ volatile unsigned char siop_sxfer; /* rw: SCSI Transfer reg */
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/*07*/ volatile unsigned char siop_scid; /* rw: SCSI Chip ID reg */
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/*08*/ volatile unsigned char siop_sbcl; /* ro: SCSI Bus Control Lines */
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/*09*/ volatile unsigned char siop_sbdl; /* ro: SCSI Bus Data Lines */
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/*0a*/ volatile unsigned char siop_sidl; /* ro: SCSI Input Data Latch */
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/*0b*/ volatile unsigned char siop_sfbr; /* ro: SCSI First Byte Received */
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/*0c*/ volatile unsigned char siop_sstat2; /* ro: SCSI status reg 2 */
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/*0d*/ volatile unsigned char siop_sstat1; /* ro: SCSI status reg 1 */
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/*0e*/ volatile unsigned char siop_sstat0; /* ro: SCSI status reg 0 */
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/*0f*/ volatile unsigned char siop_dstat; /* ro: DMA status */
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/*10*/ volatile unsigned long siop_dsa; /* rw: Data Structure Address */
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/*14*/ volatile unsigned char siop_ctest3; /* ro: Chip test register 3 */
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/*15*/ volatile unsigned char siop_ctest2; /* ro: Chip test register 2 */
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/*16*/ volatile unsigned char siop_ctest1; /* ro: Chip test register 1 */
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/*17*/ volatile unsigned char siop_ctest0; /* ro: Chip test register 0 */
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/*18*/ volatile unsigned char siop_ctest7; /* rw: Chip test register 7 */
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/*19*/ volatile unsigned char siop_ctest6; /* rw: Chip test register 6 */
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/*1a*/ volatile unsigned char siop_ctest5; /* rw: Chip test register 5 */
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/*1b*/ volatile unsigned char siop_ctest4; /* rw: Chip test register 4 */
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/*1c*/ volatile unsigned long siop_temp; /* rw: Temporary Stack reg */
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/*20*/ volatile unsigned char siop_lcrc; /* rw: LCRC value */
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/*21*/ volatile unsigned char siop_ctest8; /* rw: Chip test register 8 */
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/*22*/ volatile unsigned char siop_istat; /* rw: Interrupt Status reg */
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/*23*/ volatile unsigned char siop_dfifo; /* rw: DMA FIFO */
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/*24*/ volatile unsigned char siop_dcmd; /* rw: DMA Command Register */
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/*25*/ volatile unsigned char siop_dbc2; /* rw: DMA Byte Counter reg */
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/*26*/ volatile unsigned char siop_dbc1;
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/*27*/ volatile unsigned char siop_dbc0;
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/*28*/ volatile unsigned long siop_dnad; /* rw: DMA Next Address */
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/*2c*/ volatile unsigned long siop_dsp; /* rw: DMA SCRIPTS Pointer reg */
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/*30*/ volatile unsigned long siop_dsps; /* rw: DMA SCRIPTS Pointer Save reg */
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/*34*/ volatile unsigned long siop_scratch; /* rw: Scratch Register */
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/*38*/ volatile unsigned char siop_dcntl; /* rw: DMA Control reg */
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/*39*/ volatile unsigned char siop_dwt; /* rw: DMA Watchdog Timer */
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/*3a*/ volatile unsigned char siop_dien; /* rw: DMA Interrupt Enable */
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/*3b*/ volatile unsigned char siop_dmode; /* rw: DMA Mode reg */
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/*3c*/ volatile unsigned long siop_adder;
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#else
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/*00*/ volatile unsigned char siop_scntl3; /* rw: SCSI control reg 3 */
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/*01*/ volatile unsigned char siop_scntl2; /* rw: SCSI control reg 2 */
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/*02*/ volatile unsigned char siop_scntl1; /* rw: SCSI control reg 1 */
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/*03*/ volatile unsigned char siop_scntl0; /* rw: SCSI control reg 0 */
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/*04*/ volatile unsigned char siop_gpreg; /* rw: SCSI */
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/*05*/ volatile unsigned char siop_sdid; /* rw: SCSI Destination ID */
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/*06*/ volatile unsigned char siop_sxfer; /* rw: SCSI Transfer reg */
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/*07*/ volatile unsigned char siop_scid; /* rw: SCSI Chip ID reg */
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/*08*/ volatile unsigned char siop_sbcl; /* ro: SCSI Bus Control Lines */
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/*09*/ volatile unsigned char siop_ssid; /* ro: SCSI */
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/*0a*/ volatile unsigned char siop_socl; /* rw: SCSI Output Control Latch */
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/*0b*/ volatile unsigned char siop_sfbr; /* ro: SCSI First Byte Received */
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/*0c*/ volatile unsigned char siop_sstat2; /* ro: SCSI status reg 2 */
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/*0d*/ volatile unsigned char siop_sstat1; /* ro: SCSI status reg 1 */
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/*0e*/ volatile unsigned char siop_sstat0; /* ro: SCSI status reg 0 */
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/*0f*/ volatile unsigned char siop_dstat; /* ro: DMA status */
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/*10*/ volatile unsigned long siop_dsa; /* rw: Data Structure Address */
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/*14*/ volatile unsigned char siop_14_; /* ??: */
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/*15*/ volatile unsigned char siop_15_; /* ??: */
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/*16*/ volatile unsigned char siop_16_; /* ??: */
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/*17*/ volatile unsigned char siop_istat; /* rw: Interrupt Status reg */
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/*18*/ volatile unsigned char siop_ctest3; /* ro: Chip test register 3 */
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/*19*/ volatile unsigned char siop_ctest2; /* ro: Chip test register 2 */
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/*1a*/ volatile unsigned char siop_ctest1; /* ro: Chip test register 1 */
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/*1b*/ volatile unsigned char siop_ctest0; /* ro: Chip test register 0 */
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/*1c*/ volatile unsigned long siop_temp; /* rw: Temporary Stack reg */
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/*20*/ volatile unsigned char siop_ctest6; /* rw: Chip test register 6 */
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/*21*/ volatile unsigned char siop_ctest5; /* rw: Chip test register 5 */
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/*22*/ volatile unsigned char siop_ctest4; /* rw: Chip test register 4 */
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/*23*/ volatile unsigned char siop_dfifo; /* rw: DMA FIFO */
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/*24*/ volatile unsigned char siop_dcmd; /* rw: DMA Command Register */
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/*25*/ volatile unsigned char siop_dbc2; /* rw: DMA Byte Counter reg */
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/*26*/ volatile unsigned char siop_dbc1;
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/*27*/ volatile unsigned char siop_dbc0;
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/*28*/ volatile unsigned long siop_dnad; /* rw: DMA Next Address */
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/*2c*/ volatile unsigned long siop_dsp; /* rw: DMA SCRIPTS Pointer reg */
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/*30*/ volatile unsigned long siop_dsps; /* rw: DMA SCRIPTS Pointer Save reg */
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/*34*/ volatile unsigned long siop_scratcha; /* rw: Scratch Register A */
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/*38*/ volatile unsigned char siop_dcntl; /* rw: DMA Control reg */
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/*39*/ volatile unsigned char siop_dwt; /* rw: DMA Watchdog Timer */
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/*3a*/ volatile unsigned char siop_dien; /* rw: DMA Interrupt Enable */
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/*3b*/ volatile unsigned char siop_dmode; /* rw: DMA Mode reg */
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/*3c*/ volatile unsigned long siop_adder;
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/*40*/ volatile unsigned short siop_sist; /* rw: SCSI Interrupt Status */
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#define SIOP_SIST_STO 0x0400 /* timeout (select) */
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#define SIOP_SIST_GEN 0x0200 /* timeout (general) */
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#define SIOP_SIST_HTH 0x0100 /* handshake timer expired */
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#define SIOP_SIST_MA 0x0080 /* phase mismatch */
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#define SIOP_SIST_CMP 0x0040 /* function complete */
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#define SIOP_SIST_SEL 0x0020 /* selected */
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#define SIOP_SIST_RSL 0x0010 /* reselected */
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#define SIOP_SIST_SGE 0x0008 /* gross error (over/underflow) */
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#define SIOP_SIST_UDC 0x0004 /* unexpected disconnect */
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#define SIOP_SIST_RST 0x0002 /* RST received */
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#define SIOP_SIST_PAR 0x0001 /* scsi parity error */
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/*42*/ volatile unsigned short siop_sien; /* rw: SCSI Interrupt Enable */
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#define SIOP_SIEN_STO 0x0400 /* timeout (select) */
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#define SIOP_SIEN_GEN 0x0200 /* timeout (general) */
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#define SIOP_SIEN_HTH 0x0100 /* handshake timer expired */
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#define SIOP_SIEN_MA 0x0080 /* phase mispatch */
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#define SIOP_SIEN_CMP 0x0040 /* function complete */
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#define SIOP_SIEN_SEL 0x0020 /* selected */
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#define SIOP_SIEN_RSL 0x0010 /* reselected */
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#define SIOP_SIEN_SGE 0x0008 /* gross error (over/underflow) */
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#define SIOP_SIEN_UDC 0x0004 /* unexpected disconnect */
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#define SIOP_SIEN_RST 0x0002 /* scsi bus reset */
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#define SIOP_SIEN_PAR 0x0001 /* scsi parity error */
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/*44*/ volatile unsigned char siop_gpcntl; /* rw: SCSI */
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/*45*/ volatile unsigned char siop_macntl; /* rw: SCSI */
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/*46*/ volatile unsigned char siop_swide; /* rw: SCSI */
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/*47*/ volatile unsigned char siop_slpar; /* rw: SCSI */
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/*48*/ volatile unsigned short siop_respid; /* rw: SCSI Reselect-IDS */
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/*4a*/ volatile unsigned char siop_stime1; /* rw: SCSI */
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/*4b*/ volatile unsigned char siop_stime0; /* rw: SCSI */
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/*4c*/ volatile unsigned char siop_stest3; /* ro: Chip test register 3 */
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#define SIOP_STEST3_HSC 0x20 /* Halt SCSI Clock */
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/*4d*/ volatile unsigned char siop_stest2; /* ro: Chip test register 2 */
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/*4e*/ volatile unsigned char siop_stest1; /* ro: Chip test register 1 */
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#define SIOP_STEST1_DBLEN 0x08 /* SCLK Double Enable */
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#define SIOP_STEST1_DBLSEL 0x04 /* SCLK Doubler Select */
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/*4f*/ volatile unsigned char siop_stest0; /* ro: Chip test register 0 */
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/*50*/ volatile unsigned char siop_50_; /* rw: SCSI */
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/*51*/ volatile unsigned char siop_stest4; /* rw: SCSI */
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/*52*/ volatile unsigned short siop_sidl; /* ro: SCSI Input Data Latch */
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/*54*/ volatile unsigned short siop_54_; /* rw: SCSI */
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/*56*/ volatile unsigned short siop_sodl; /* rw: SCSI Output Data Latch */
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/*58*/ volatile unsigned short siop_58_; /* rw: SCSI */
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/*5a*/ volatile unsigned short siop_sbdl; /* ro: SCSI Bus Data Lines */
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/*5c*/ volatile unsigned long siop_scratchb; /* rw: Scratch Register B */
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#endif
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} siop_regmap_t;
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typedef volatile siop_regmap_t *siop_regmap_p;
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/*
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* Register defines
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*/
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/* Scsi control register 0 (scntl0) */
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#define SIOP_SCNTL0_ARB 0xc0 /* Arbitration mode */
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# define SIOP_ARB_SIMPLE 0x00
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# define SIOP_ARB_FULL 0xc0
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#define SIOP_SCNTL0_START 0x20 /* Start Sequence */
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#define SIOP_SCNTL0_WATN 0x10 /* (Select) With ATN */
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#define SIOP_SCNTL0_EPC 0x08 /* Enable Parity Checking */
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#define SIOP_SCNTL0_EPG 0x04 /* Enable Parity Generation */
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#define SIOP_SCNTL0_AAP 0x02 /* Assert ATN on Parity Error */
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#define SIOP_SCNTL0_TRG 0x01 /* Target Mode */
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/* Scsi control register 1 (scntl1) */
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#define SIOP_SCNTL1_EXC 0x80 /* Extra Clock Cycle of data setup */
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#define SIOP_SCNTL1_ADB 0x40 /* Assert Data Bus */
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#ifndef ARCH_720
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#define SIOP_SCNTL1_ESR 0x20 /* Enable Selection/Reselection */
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#else
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#define SIOP_SCNTL1_DHP 0x20 /* Disable Halt on Parity or ATN */
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#endif
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#define SIOP_SCNTL1_CON 0x10 /* Connected */
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#define SIOP_SCNTL1_RST 0x08 /* Assert RST */
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#define SIOP_SCNTL1_AESP 0x04 /* Assert even SCSI parity */
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#ifndef ARCH_720
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#define SIOP_SCNTL1_RES0 0x02 /* Reserved */
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#define SIOP_SCNTL1_RES1 0x01 /* Reserved */
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#else
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#define SIOP_SCNTL1_IARB 0x02 /* Immediate Arbitration */
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#define SIOP_SCNTL1_SST 0x01 /* Start SCSI Transfer */
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#endif
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/* Scsi control register 3 (scntl3) */
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#ifdef ARCH_720
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#define SIOP_SCNTL3_ULTRA 0x80 /* Ultra Enable */
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#define SIOP_SCNTL3_SCF 0x70 /* Synch Clock Conversion Factor */
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#define SIOP_SCNTL3_EWS 0x08 /* Enable Wide SCSI */
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#define SIOP_SCNTL3_CCF 0x07 /* Clock Conversion Factor */
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#endif
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/* Scsi interrupt enable register (sien) */
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#ifndef ARCH_720
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#define SIOP_SIEN_M_A 0x80 /* Phase Mismatch or ATN active */
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#define SIOP_SIEN_FCMP 0x40 /* Function Complete */
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#define SIOP_SIEN_STO 0x20 /* (Re)Selection timeout */
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#define SIOP_SIEN_SEL 0x10 /* (Re)Selected */
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#define SIOP_SIEN_SGE 0x08 /* SCSI Gross Error */
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#define SIOP_SIEN_UDC 0x04 /* Unexpected Disconnect */
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#define SIOP_SIEN_RST 0x02 /* RST asserted */
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#define SIOP_SIEN_PAR 0x01 /* Parity Error */
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#endif
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/* Scsi chip ID (scid) */
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#define SIOP_SCID_VALUE(i) (1<<i)
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#ifdef ARCH_720
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#define SIOP_SCID_RRE 0x40 /* Enable Response to Reselection */
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#define SIOP_SCID_SRE 0x20 /* Enable Response to Selection */
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#endif
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/* Scsi transfer register (sxfer) */
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#ifndef ARCH_720
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#define SIOP_SXFER_DHP 0x80 /* Disable Halt on Parity error/ ATN asserted */
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#define SIOP_SXFER_TP 0x70 /* Synch Transfer Period */
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/* see specs for formulas:
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Period = TCP * (4 + XFERP )
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TCP = 1 + CLK + 1..2;
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*/
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#define SIOP_SXFER_MO 0x0f /* Synch Max Offset */
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# define SIOP_MAX_OFFSET 8
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#else
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#define SIOP_SXFER_TP 0xe0 /* Synch Transfer Period */
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/* see specs for formulas:
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Period = TCP * (4 + XFERP )
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TCP = 1 + CLK + 1..2;
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*/
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#define SIOP_SXFER_MO 0x1f /* Synch Max Offset */
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# define SIOP_MAX_OFFSET 16
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#endif
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/* Scsi output data latch register (sodl) */
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/* Scsi output control latch register (socl) */
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#define SIOP_REQ 0x80 /* SCSI signal <x> asserted */
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#define SIOP_ACK 0x40
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#define SIOP_BSY 0x20
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#define SIOP_SEL 0x10
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#define SIOP_ATN 0x08
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#define SIOP_MSG 0x04
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#define SIOP_CD 0x02
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#define SIOP_IO 0x01
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#define SIOP_PHASE(socl) SCSI_PHASE(socl)
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/* Scsi first byte received register (sfbr) */
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/* Scsi input data latch register (sidl) */
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/* Scsi bus data lines register (sbdl) */
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/* Scsi bus control lines register (sbcl). Same as socl */
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/* DMA status register (dstat) */
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#define SIOP_DSTAT_DFE 0x80 /* DMA FIFO empty */
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#ifndef ARCH_720
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#define SIOP_DSTAT_RES 0x40
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#else
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#define SIOP_DSTAT_HPE 0x40 /* Host Parity Error */
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#endif
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#define SIOP_DSTAT_BF 0x20 /* Bus fault */
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#define SIOP_DSTAT_ABRT 0x10 /* Aborted */
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#define SIOP_DSTAT_SSI 0x08 /* SCRIPT Single Step */
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#define SIOP_DSTAT_SIR 0x04 /* SCRIPT Interrupt Instruction */
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#define SIOP_DSTAT_WTD 0x02 /* Watchdog Timeout Detected */
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#define SIOP_DSTAT_IID 0x01 /* Invalid Instruction Detected */
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/* Scsi status register 0 (sstat0) */
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#ifndef ARCH_720
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#define SIOP_SSTAT0_M_A 0x80 /* Phase Mismatch or ATN active */
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#define SIOP_SSTAT0_FCMP 0x40 /* Function Complete */
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#define SIOP_SSTAT0_STO 0x20 /* (Re)Selection timeout */
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#define SIOP_SSTAT0_SEL 0x10 /* (Re)Selected */
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#define SIOP_SSTAT0_SGE 0x08 /* SCSI Gross Error */
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#define SIOP_SSTAT0_UDC 0x04 /* Unexpected Disconnect */
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#define SIOP_SSTAT0_RST 0x02 /* RST asserted */
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#define SIOP_SSTAT0_PAR 0x01 /* Parity Error */
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#else
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#define SIOP_SSTAT0_ILF 0x80 /* SIDL lsb full */
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#define SIOP_SSTAT0_ORF 0x40 /* SODR lsb full */
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#define SIOP_SSTAT0_OLF 0x20 /* SODL lsb full */
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#define SIOP_SSTAT0_AIP 0x10 /* Arbitration in progress */
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#define SIOP_SSTAT0_LOA 0x08 /* Lost Arbitration */
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#define SIOP_SSTAT0_WOA 0x04 /* Won Arbitration */
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#define SIOP_SSTAT0_RST 0x02 /* SCSI RST/ signal */
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#define SIOP_SSTAT0_SDP0 0x01 /* SCSI SDP0/ parity signal */
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#endif
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/* Scsi status register 1 (sstat1) */
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#ifndef ARCH_720
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#define SIOP_SSTAT1_ILF 0x80 /* Input latch (sidl) full */
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#define SIOP_SSTAT1_ORF 0x40 /* output reg (sodr) full */
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#define SIOP_SSTAT1_OLF 0x20 /* output latch (sodl) full */
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#define SIOP_SSTAT1_AIP 0x10 /* Arbitration in progress */
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#define SIOP_SSTAT1_LOA 0x08 /* Lost arbitration */
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#define SIOP_SSTAT1_WOA 0x04 /* Won arbitration */
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#define SIOP_SSTAT1_RST 0x02 /* SCSI RST current value */
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#define SIOP_SSTAT1_SDP 0x01 /* SCSI SDP current value */
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#else
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#define SIOP_SSTAT1_FF 0xf0 /* SCSI FIFO flags (bytecount) */
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#define SIOP_SSTAT1_SDP0 0x08 /* Latched (on REQ) SCSI Parity */
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#define SIOP_SSTAT1_MSG 0x04 /* Latched SCSI phase */
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#define SIOP_SSTAT1_CD 0x02
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#define SIOP_SSTAT1_IO 0x01
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#endif
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/* Scsi status register 2 (sstat2) */
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#ifndef ARCH_720
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#define SIOP_SSTAT2_FF 0xf0 /* SCSI FIFO flags (bytecount) */
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# define SIOP_SCSI_FIFO_DEEP 8
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#define SIOP_SSTAT2_SDP 0x08 /* Latched (on REQ) SCSI SDP */
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#define SIOP_SSTAT2_MSG 0x04 /* Latched SCSI phase */
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#define SIOP_SSTAT2_CD 0x02
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#define SIOP_SSTAT2_IO 0x01
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#else
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#define SIOP_SSTAT2_ILF1 0x80 /* SIDL msb full */
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#define SIOP_SSTAT2_ORF1 0x40 /* SODR msb full */
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#define SIOP_SSTAT2_OLF1 0x20 /* SODL msb full */
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#define SIOP_SSTAT2_FF4 0x10 /* FIFO flags bit 4 */
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#define SIOP_SSTAT2_SPL1 0x08 /* Latched Parity for SD15-8 */
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#define SIOP_SSTAT2_DIFF 0x04 /* DIFFSENSE Sense */
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#define SIOP_SSTAT2_LDSC 0x02 /* Last Disconnect */
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#define SIOP_SSTAT2_SDP1 0x01 /* SCSI SDP1 Parity */
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#endif
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/* Chip test register 0 (ctest0) */
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#ifndef ARCH_720
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#define SIOP_CTEST0_RES0 0x80
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#define SIOP_CTEST0_BTD 0x40 /* Byte-to-byte Timer Disable */
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#define SIOP_CTEST0_GRP 0x20 /* Generate Receive Parity for Passthrough */
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#define SIOP_CTEST0_EAN 0x10 /* Enable Active Negation */
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#define SIOP_CTEST0_HSC 0x08 /* Halt SCSI clock */
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#define SIOP_CTEST0_ERF 0x04 /* Extend REQ/ACK Filtering */
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#define SIOP_CTEST0_RES1 0x02
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#define SIOP_CTEST0_DDIR 0x01 /* Xfer direction (1-> from SCSI bus) */
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#endif
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/* Chip test register 1 (ctest1) */
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#define SIOP_CTEST1_FMT 0xf0 /* Byte empty in DMA FIFO bottom (high->byte3) */
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#define SIOP_CTEST1_FFL 0x0f /* Byte full in DMA FIFO top, same */
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/* Chip test register 2 (ctest2) */
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#ifndef ARCH_720
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#define SIOP_CTEST2_RES 0x80
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#else
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#define SIOP_CTETS2_DDIR 0x80 /* Data Transfer Direction */
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#endif
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#define SIOP_CTEST2_SIGP 0x40 /* Signal process */
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#ifndef ARCH_720
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#define SIOP_CTEST2_SOFF 0x20 /* Synch Offset compare (1-> zero Init, max Tgt */
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#define SIOP_CTEST2_SFP 0x10 /* SCSI FIFO Parity */
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#else
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#define SIOP_CTEST2_RES5 0x20
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#define SIOP_CTEST2_RES4 0x10
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#endif
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#define SIOP_CTEST2_DFP 0x08 /* DMA FIFO Parity */
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#define SIOP_CTEST2_TEOP 0x04 /* True EOP (a-la 5380) */
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#define SIOP_CTEST2_DREQ 0x02 /* DREQ status */
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#define SIOP_CTEST2_DACK 0x01 /* DACK status */
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/* Chip test register 3 (ctest3) read-only, top of SCSI FIFO */
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#ifdef ARCH_720
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#define SIOP_CTEST3_V 0xf0 /* Chip revision level */
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#define SIOP_CTEST3_FLF 0x08 /* Flush DMA FIFO */
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#define SIOP_CTEST3_CLF 0x04 /* Clear DMA FIFO */
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#define SIOP_CTEST3_FM 0x02 /* Fetch pin mode */
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#define SIOP_CTEST3_SM 0x01 /* Snoop pins mode */
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#endif
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/* Chip test register 4 (ctest4) */
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#define SIOP_CTEST4_MUX 0x80 /* Host bus multiplex mode */
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#define SIOP_CTEST4_ZMOD 0x40 /* High-impedance outputs */
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#define SIOP_CTEST4_SZM 0x20 /* ditto, SCSI "outputs" */
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#ifndef ARCH_720
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#define SIOP_CTEST4_SLBE 0x10 /* SCSI loobpack enable */
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#define SIOP_CTEST4_SFWR 0x08 /* SCSI FIFO write enable (from sodl) */
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#else
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#define SIOP_CTEST4_SRTM 0x10 /* Shadow Register Test Mode */
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#define SIOP_CTEST4_EHPC 8x08 /* Enable Host Parity Check */
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#endif
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#define SIOP_CTEST4_FBL 0x07 /* DMA FIFO Byte Lane select (from ctest6)
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4->0, .. 7->3 */
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/* Chip test register 5 (ctest5) */
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#define SIOP_CTEST5_ADCK 0x80 /* Clock Address Incrementor */
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#define SIOP_CTEST5_BBCK 0x40 /* Clock Byte counter */
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#ifndef ARCH_720
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#define SIOP_CTEST5_ROFF 0x20 /* Reset SCSI offset */
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#else
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#define SIOP_CTEST5_RES 0x20
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#endif
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#define SIOP_CTEST5_MASR 0x10 /* Master set/reset pulses (of bits 3-0) */
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#define SIOP_CTEST5_DDIR 0x08 /* (re)set internal DMA direction */
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#ifndef ARCH_720
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#define SIOP_CTEST5_EOP 0x04 /* (re)set internal EOP */
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#define SIOP_CTEST5_DREQ 0x02 /* (re)set internal REQ */
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#define SIOP_CTEST5_DACK 0x01 /* (re)set internal ACK */
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#else
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#define SIOP_CTEST5_RAM 0x06 /* SCRIPTS RAM 1-0 */
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#define SIOP_CTEST5 RAMEN 0x01 /* RAM Base Address Enable */
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#endif
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/* Chip test register 6 (ctest6) DMA FIFO access */
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/* Chip test register 7 (ctest7) */
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#ifndef ARCH_720
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#define SIOP_CTEST7_CDIS 0x80 /* Cache burst disable */
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#define SIOP_CTEST7_SC1 0x40 /* Snoop control 1 */
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#define SIOP_CTEST7_SC0 0x20 /* Snoop contorl 0 */
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#define SIOP_CTEST7_STD 0x10 /* Selection timeout disable */
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#define SIOP_CTEST7_DFP 0x08 /* DMA FIFO parity bit */
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#define SIOP_CTEST7_EVP 0x04 /* Even parity (to host bus) */
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#define SIOP_CTEST7_TT1 0x02 /* Transfer type bit */
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#define SIOP_CTEST7_DIFF 0x01 /* Differential mode */
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#endif
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/* DMA FIFO register (dfifo) */
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#define SIOP_DFIFO_RES 0x80
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#define SIOP_DFIFO_BO 0x7f /* FIFO byte offset counter */
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/* Interrupt status register (istat) */
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#define SIOP_ISTAT_ABRT 0x80 /* Abort operation */
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#define SIOP_ISTAT_RST 0x40 /* Software reset */
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#define SIOP_ISTAT_SIGP 0x20 /* Signal process */
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#ifndef ARCH_720
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#define SIOP_ISTAT_RES 0x10
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#else
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#define SIOP_ISTAT_SEM 0x10 /* Semaphore */
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#endif
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#define SIOP_ISTAT_CON 0x08 /* Connected */
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#ifndef ARCH_720
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#define SIOP_ISTAT_RES1 0x04
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#else
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#define SIOP_ISTAT_INTF 0x04 /* Interrupt on the Fly */
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#endif
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#define SIOP_ISTAT_SIP 0x02 /* SCSI Interrupt pending */
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#define SIOP_ISTAT_DIP 0x01 /* DMA Interrupt pending */
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/* Chip test register 8 (ctest8) */
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#define SIOP_CTEST8_V 0xf0 /* Chip revision level */
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#define SIOP_CTEST8_FLF 0x08 /* Flush DMA FIFO */
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#define SIOP_CTEST8_CLF 0x04 /* Clear DMA and SCSI FIFOs */
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#define SIOP_CTEST8_FM 0x02 /* Fetch pin mode */
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#define SIOP_CTEST8_SM 0x01 /* Snoop pins mode */
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/* DMA Mode register (dmode) */
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#define SIOP_DMODE_BL_MASK 0xc0 /* 0->1 1->2 2->4 3->8 */
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#define SIOP_DMODE_FC 0x30 /* Function code */
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#define SIOP_DMODE_PD 0x08 /* Program/data */
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#define SIOP_DMODE_FAM 0x04 /* Fixed address mode */
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#define SIOP_DMODE_U0 0x02 /* User programmable transfer type */
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#define SIOP_DMODE_MAN 0x01 /* Manual start mode */
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/* DMA interrupt enable register (dien) */
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|
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#define SIOP_DIEN_RES 0xc0
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#ifdef ARCH_720
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#define SIOP_DIEN_HPED 0x40 /* Host Parity */
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#endif
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#define SIOP_DIEN_BF 0x20 /* On Bus Fault */
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#define SIOP_DIEN_ABRT 0x10 /* On Abort */
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#define SIOP_DIEN_SSI 0x08 /* On SCRIPTS sstep */
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#define SIOP_DIEN_SIR 0x04 /* On SCRIPTS intr instruction */
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#define SIOP_DIEN_WTD 0x02 /* On watchdog timeout */
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#define SIOP_DIEN_IID 0x01 /* On illegal instruction detected */
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/* DMA control register (dcntl) */
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|
|
|
#ifndef ARCH_720
|
|
#define SIOP_DCNTL_CF_MASK 0xc0 /* Clock frequency dividers:
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0 --> 37.51..50.00 Mhz, div=2
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1 --> 25.01..37.50 Mhz, div=1.5
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2 --> 16.67..25.00 Mhz, div=1
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3 --> 50.01..66.67 Mhz, div=3
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*/
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#else
|
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#define SIOP_DCNTL_STE 0x80 /* Size Throttle Enable */
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#define SIOP_DCNTL_BSM 0x40 /* Bus Mode */
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#endif
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#define SIOP_DCNTL_EA 0x20 /* Enable ack */
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|
#define SIOP_DCNTL_SSM 0x10 /* Single step mode */
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|
#ifndef ARCH_720
|
|
#define SIOP_DCNTL_LLM 0x08 /* Enable SCSI Low-level mode */
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|
#else
|
|
#define SIOP_DCNTL_BW16 0x8 /* Bus Width 16 */
|
|
#endif
|
|
#define SIOP_DCNTL_STD 0x04 /* Start DMA operation */
|
|
#define SIOP_DCNTL_FA 0x02 /* Fast arbitration */
|
|
#define SIOP_DCNTL_COM 0x01 /* 53C700 compatibility */
|