NetBSD/sys/arch/x68k/dev/zs.c

510 lines
11 KiB
C

/* $NetBSD: zs.c,v 1.12 1998/08/05 16:08:36 minoura Exp $ */
/*-
* Copyright (c) 1998 Minoura Makoto
* Copyright (c) 1996 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Gordon W. Ross.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the NetBSD
* Foundation, Inc. and its contributors.
* 4. Neither the name of The NetBSD Foundation nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Zilog Z8530 Dual UART driver (machine-dependent part)
*
* X68k uses one Z8530 built-in. Channel A is for RS-232C serial port;
* while channel B is dedicated to the mouse.
* Extra Z8530's can be installed. This driver supports up to 5 chips
* including the built-in one.
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/conf.h>
#include <sys/device.h>
#include <sys/file.h>
#include <sys/ioctl.h>
#include <sys/kernel.h>
#include <sys/proc.h>
#include <sys/tty.h>
#include <sys/time.h>
#include <sys/syslog.h>
#include <machine/cpu.h>
#include <machine/z8530var.h>
/*#include <arch/x68k/x68k/iodevice.h>*/
#include <dev/ic/z8530reg.h>
#include "zsc.h" /* NZSC */
#include "zstty.h"
/* Make life easier for the initialized arrays here. */
extern void Debugger __P((void));
/*
* Some warts needed by z8530tty.c -
* The default parity REALLY needs to be the same as the PROM uses,
* or you can not see messages done with printf during boot-up...
*/
int zs_def_cflag = (CREAD | CS8 | HUPCL);
int zs_major = 12;
/*
* X68k provides a 5.0 MHz clock to the ZS chips.
* XXX: use 4.9152MHz constant for now!!!
*/
#define PCLK (9600 * 512) /* PCLK pin input clock rate */
static u_char zs_init_reg[16] = {
0, /* 0: CMD (reset, etc.) */
0, /* 1: No interrupts yet. */
0x70, /* 2: XXX: IVECT */
ZSWR3_RX_8 | ZSWR3_RX_ENABLE,
ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP,
ZSWR5_TX_8 | ZSWR5_TX_ENABLE,
0, /* 6: TXSYNC/SYNCLO */
0, /* 7: RXSYNC/SYNCHI */
0, /* 8: alias for data port */
ZSWR9_MASTER_IE,
ZSWR10_NRZ, /*10: Misc. TX/RX control bits */
ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD,
14, /*12: BAUDLO (default=9600) */
0, /*13: BAUDHI (default=9600) */
ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK,
ZSWR15_BREAK_IE | ZSWR15_DCD_IE,
};
static volatile struct zschan *conschan = 0;
/****************************************************************
* Autoconfig
****************************************************************/
/* Definition of the driver for autoconfig. */
static int zs_match __P((struct device *, struct cfdata *, void *));
static void zs_attach __P((struct device *, struct device *, void *));
static int zs_print __P((void *, const char *name));
struct cfattach zsc_ca = {
sizeof(struct zsc_softc), zs_match, zs_attach
};
extern struct cfdriver zsc_cd;
static volatile struct zsdevice *findzs(int);
int zshard __P((void));
int zssoft __P((void *));
static int zs_get_speed __P((struct zs_chanstate *));
/*
* find zs address for x68k architecture
*/
static volatile struct zsdevice *
findzs(zs)
int zs;
{
if (zs == 0)
return &IODEVbase->io_inscc;
if (1 <= zs && zs <= 4)
return &(IODEVbase->io_exscc)[zs - 1];
/* none */
return 0;
}
/*
* Is the zs chip present?
*/
static int
zs_match(parent, cfp, aux)
struct device *parent;
struct cfdata *cfp;
void *aux;
{
volatile void *addr;
if(strcmp("zs", aux) || (addr = findzs(cfp->cf_unit)) == 0)
return(0);
if (badaddr(addr))
return 0;
return(1);
}
/*
* Attach a found zs.
*/
static void
zs_attach(parent, self, aux)
struct device *parent;
struct device *self;
void *aux;
{
struct zsc_softc *zsc = (void *) self;
struct zsc_attach_args zsc_args;
volatile struct zschan *zc;
struct zs_chanstate *cs;
int s, zs_unit, channel;
zs_unit = zsc->zsc_dev.dv_unit;
zsc->zsc_addr = (void*) findzs (zs_unit);
printf("\n");
/*
* Initialize software state for each channel.
*/
for (channel = 0; channel < 2; channel++) {
struct device *child;
zsc_args.channel = channel;
zsc_args.hwflags = 0;
cs = &zsc->zsc_cs_store[channel];
zsc->zsc_cs[channel] = cs;
cs->cs_channel = channel;
cs->cs_private = NULL;
cs->cs_ops = &zsops_null;
cs->cs_brg_clk = PCLK / 16;
if (channel == 0)
zc = (void*) &zsc->zsc_addr->zs_chan_a;
else
zc = (void*) &zsc->zsc_addr->zs_chan_b;
cs->cs_reg_csr = &zc->zc_csr;
cs->cs_reg_data = &zc->zc_data;
zs_init_reg[2] = 0x70 + zs_unit;
bcopy(zs_init_reg, cs->cs_creg, 16);
bcopy(zs_init_reg, cs->cs_preg, 16);
cs->cs_defspeed = 9600;
cs->cs_defcflag = zs_def_cflag;
/* Make these correspond to cs_defcflag (-crtscts) */
cs->cs_rr0_dcd = ZSRR0_DCD;
cs->cs_rr0_cts = 0;
cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;
cs->cs_wr5_rts = 0;
/*
* Clear the master interrupt enable.
* The INTENA is common to both channels,
* so just do it on the A channel.
*/
if (channel == 0) {
s = splzs();
zs_write_reg(cs, 9, 0);
splx(s);
}
/*
* Look for a child driver for this channel.
* The child attach will setup the hardware.
*/
child = config_found(self, (void *)&zsc_args, zs_print);
if (child == NULL) {
/* No sub-driver. Just reset it. */
u_char reset = (channel == 0) ?
ZSWR9_A_RESET : ZSWR9_B_RESET;
s = splzs();
zs_write_reg(cs, 9, reset);
splx(s);
}
}
/*
* Set the master interrupt enable and interrupt vector.
* (common to both channels, do it on A)
*/
cs = zsc->zsc_cs[0];
s = splzs();
/* interrupt vector */
zs_write_reg(cs, 2, 0x70 + zs_unit);
/* master interrupt control (enable) */
zs_write_reg(cs, 9, zs_init_reg[9]);
splx(s);
}
static int
zs_print(aux, name)
void *aux;
const char *name;
{
struct zsc_attach_args *args = aux;
if (name != NULL)
printf("%s: ", name);
if (args->channel != -1)
printf(" channel %d", args->channel);
return UNCONF;
}
static volatile int zssoftpending;
/*
* Our ZS chips all share a common, autovectored interrupt,
* so we have to look at all of them on each interrupt.
*/
int
zshard(void)
{
register struct zsc_softc *zsc;
register int unit, rval, softreq;
rval = softreq = 0;
for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) {
zsc = zsc_cd.cd_devs[unit];
if (zsc == NULL)
continue;
rval |= zsc_intr_hard(zsc);
softreq |= zsc->zsc_cs[0]->cs_softreq;
softreq |= zsc->zsc_cs[1]->cs_softreq;
}
/* We are at splzs here, so no need to lock. */
if (softreq && (zssoftpending == 0)) {
zssoftpending = 1;
setsoftserial();
}
return (rval);
}
/*
* Similar scheme as for zshard (look at all of them)
*/
int
zssoft(arg)
void *arg;
{
register struct zsc_softc *zsc;
register int s, unit;
/* This is not the only ISR on this IPL. */
if (zssoftpending == 0)
return (0);
zssoftpending = 0;
/* Make sure we call the tty layer at spltty. */
s = spltty();
for (unit = 0; unit < zsc_cd.cd_ndevs; unit++) {
zsc = zsc_cd.cd_devs[unit];
if (zsc == NULL)
continue;
(void) zsc_intr_soft(zsc);
}
splx(s);
return (1);
}
/*
* Compute the current baud rate given a ZS channel.
*/
static int
zs_get_speed(cs)
struct zs_chanstate *cs;
{
int tconst;
tconst = zs_read_reg(cs, 12);
tconst |= zs_read_reg(cs, 13) << 8;
return (TCONST_TO_BPS(cs->cs_brg_clk, tconst));
}
/*
* MD functions for setting the baud rate and control modes.
*/
int
zs_set_speed(cs, bps)
struct zs_chanstate *cs;
int bps; /* bits per second */
{
int tconst, real_bps;
if (bps == 0)
return (0);
#ifdef DIAGNOSTIC
if (cs->cs_brg_clk == 0)
panic("zs_set_speed");
#endif
tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps);
if (tconst < 0)
return (EINVAL);
/* Convert back to make sure we can do it. */
real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst);
/* XXX - Allow some tolerance here? */
if (real_bps != bps)
return (EINVAL);
cs->cs_preg[12] = tconst;
cs->cs_preg[13] = tconst >> 8;
/* Caller will stuff the pending registers. */
return (0);
}
int
zs_set_modes(cs, cflag)
struct zs_chanstate *cs;
int cflag; /* bits per second */
{
int s;
/*
* Output hardware flow control on the chip is horrendous:
* if carrier detect drops, the receiver is disabled, and if
* CTS drops, the transmitter is stoped IN MID CHARACTER!
* Therefore, NEVER set the HFC bit, and instead use the
* status interrupt to detect CTS changes.
*/
s = splzs();
if ((cflag & (CLOCAL | MDMBUF)) != 0)
cs->cs_rr0_dcd = 0;
else
cs->cs_rr0_dcd = ZSRR0_DCD;
if ((cflag & CRTSCTS) != 0) {
cs->cs_wr5_dtr = ZSWR5_DTR;
cs->cs_wr5_rts = ZSWR5_RTS;
cs->cs_rr0_cts = ZSRR0_CTS;
} else if ((cflag & MDMBUF) != 0) {
cs->cs_wr5_dtr = 0;
cs->cs_wr5_rts = ZSWR5_DTR;
cs->cs_rr0_cts = ZSRR0_DCD;
} else {
cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;
cs->cs_wr5_rts = 0;
cs->cs_rr0_cts = 0;
}
splx(s);
/* Caller will stuff the pending registers. */
return (0);
}
/*
* Read or write the chip with suitable delays.
*/
u_char
zs_read_reg(cs, reg)
struct zs_chanstate *cs;
u_char reg;
{
u_char val;
*cs->cs_reg_csr = reg;
ZS_DELAY();
val = *cs->cs_reg_csr;
ZS_DELAY();
return val;
}
void
zs_write_reg(cs, reg, val)
struct zs_chanstate *cs;
u_char reg, val;
{
*cs->cs_reg_csr = reg;
ZS_DELAY();
*cs->cs_reg_csr = val;
ZS_DELAY();
}
u_char zs_read_csr(cs)
struct zs_chanstate *cs;
{
register u_char val;
val = *cs->cs_reg_csr;
ZS_DELAY();
return val;
}
void zs_write_csr(cs, val)
struct zs_chanstate *cs;
u_char val;
{
*cs->cs_reg_csr = val;
ZS_DELAY();
}
u_char zs_read_data(cs)
struct zs_chanstate *cs;
{
register u_char val;
val = *cs->cs_reg_data;
ZS_DELAY();
return val;
}
void zs_write_data(cs, val)
struct zs_chanstate *cs;
u_char val;
{
*cs->cs_reg_data = val;
ZS_DELAY();
}
/*
* Handle user request to enter kernel debugger.
*/
void
zs_abort(cs)
struct zs_chanstate *cs;
{
int rr0;
/* Wait for end of break to avoid PROM abort. */
/* XXX - Limit the wait? */
do {
rr0 = *cs->cs_reg_csr;
ZS_DELAY();
} while (rr0 & ZSRR0_BREAK);
#ifdef DDB
Debugger();
#else
printf ("BREAK!!\n");
#endif
}