179 lines
5.1 KiB
C
179 lines
5.1 KiB
C
/* $NetBSD: if_le_dec.c,v 1.10 1998/07/21 17:36:05 drochner Exp $ */
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/*-
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* Copyright (c) 1997 Jonathan Stone. All rights reserved.
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* Copyright (c) 1995 Charles M. Hannum. All rights reserved.
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* Ralph Campbell and Rick Macklem.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)if_le.c 8.2 (Berkeley) 11/16/93
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*/
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#include "opt_inet.h"
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#include "bpfilter.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/mbuf.h>
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#include <sys/syslog.h>
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#include <sys/socket.h>
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#include <sys/device.h>
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#include <net/if.h>
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#include <net/if_ether.h>
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#include <net/if_media.h>
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#ifdef INET
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#include <netinet/in.h>
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#include <netinet/if_inarp.h>
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#endif
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#include <dev/ic/lancereg.h>
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#include <dev/ic/lancevar.h>
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#include <dev/ic/am7990reg.h>
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#include <dev/ic/am7990var.h>
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#include <dev/tc/if_levar.h>
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#include <dev/tc/tcvar.h>
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#include <machine/bus.h>
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/* access LANCE registers */
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void le_dec_writereg __P((volatile u_short *regptr, u_short val));
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#define LERDWR(cntl, src, dst) { (dst) = (src); tc_mb(); }
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#define LEWREG(src, dst) le_dec_writereg(&(dst), (src))
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#if defined(_KERNEL) && !defined(_LKM)
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#include "opt_ddb.h"
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#endif
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#ifdef DDB
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#define integrate
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#define hide
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#else
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#define integrate static __inline
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#define hide static
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#endif
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hide void le_dec_wrcsr __P((struct lance_softc *, u_int16_t, u_int16_t));
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hide u_int16_t le_dec_rdcsr __P((struct lance_softc *, u_int16_t));
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void
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dec_le_common_attach(sc, eap)
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struct am7990_softc *sc;
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u_char *eap;
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{
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int i;
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sc->lsc.sc_rdcsr = le_dec_rdcsr;
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sc->lsc.sc_wrcsr = le_dec_wrcsr;
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sc->lsc.sc_hwinit = NULL;
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sc->lsc.sc_conf3 = 0;
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sc->lsc.sc_addr = 0;
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sc->lsc.sc_memsize = 65536;
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/*
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* Get the ethernet address out of rom
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*/
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for (i = 0; i < sizeof(sc->lsc.sc_enaddr); i++) {
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sc->lsc.sc_enaddr[i] = *eap;
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eap += 4;
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}
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am7990_config(sc);
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}
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hide void
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le_dec_wrcsr(sc, port, val)
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struct lance_softc *sc;
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u_int16_t port, val;
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{
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struct lereg1 *ler1 = ((struct le_softc *)sc)->sc_r1;
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LEWREG(port, ler1->ler1_rap);
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LERDWR(port, val, ler1->ler1_rdp);
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}
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hide u_int16_t
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le_dec_rdcsr(sc, port)
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struct lance_softc *sc;
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u_int16_t port;
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{
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struct lereg1 *ler1 = ((struct le_softc *)sc)->sc_r1;
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u_int16_t val;
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LEWREG(port, ler1->ler1_rap);
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LERDWR(0, ler1->ler1_rdp, val);
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return (val);
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}
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/*
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* Write a lance register port, reading it back to ensure success. This seems
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* to be necessary during initialization, since the chip appears to be a bit
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* pokey sometimes.
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*/
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void
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le_dec_writereg(regptr, val)
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register volatile u_short *regptr;
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register u_short val;
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{
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register int i = 0;
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while (*regptr != val) {
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*regptr = val;
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tc_mb();
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if (++i > 10000) {
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printf("le: Reg did not settle (to x%x): x%x\n", val,
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*regptr);
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return;
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}
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DELAY(100);
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}
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}
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/*
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* Routines for accessing the transmit and receive buffers are provided
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* by am7990.c, because of the LE_NEED_BUF_* macros defined above.
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* Unfortunately, CPU addressing of these buffers is done in one of
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* 3 ways:
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* - contiguous (for the 3max and turbochannel option card)
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* - gap2, which means shorts (2 bytes) interspersed with short (2 byte)
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* spaces (for the pmax, vax 3400, and ioasic LANCE descriptors)
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* - gap16, which means 16bytes interspersed with 16byte spaces
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* for buffers which must begin on a 32byte boundary (for 3min, maxine,
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* and alpha)
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* The buffer offset is the logical byte offset, assuming contiguous storage.
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*/
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