008816ea4f
Adds (most) support for ARC platform to port-independent mips code. Some changes (e.g., clean up of overlapping CPU/FPU ids) inspired by comparison to the OpenBSD 2.1 codebase of Soda's ARC port. Open issues: * Still no support for r4600 or mipsIV CPUs with two-way L1 cache. Code derived from Per Fogelstrom's OpenBSD source doesn't work on mips3 pmaxes with L2 cache. * Still some port-specific #ifdefs, for interrupt enable and pmax L2 cache-size. Needs more thought, but overlaps with work-in-progress by Tohru and Tsubai on spl()s and related stuff.
9 lines
165 B
ArmAsm
9 lines
165 B
ArmAsm
/* $NetBSD: memcpy.S,v 1.1 1998/09/11 16:46:34 jonathan Exp $ */
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#include <mips/asm.h>
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#include <machine/endian.h>
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.data
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.globl __no_memcpy
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__no_memcpy: .word 0
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