177 lines
7.0 KiB
C
177 lines
7.0 KiB
C
/* $NetBSD: if_aumacreg.h,v 1.1 2002/07/29 15:39:14 simonb Exp $ */
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/*
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* Copyright (c) 2001 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Jason R. Thorpe for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _MIPS_ALCHEMY_DEV_AUMACREG_H_
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#define _MIPS_ALCHEMY_DEV_AUMACREG_H_
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/*
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* Register description for the Alchemy Semiconductor Au1X00
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* Ethernet Media Access Controllers.
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*/
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#define MAC_BUFLEN 0x0800
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#define MAC_BUFLEN_JUMBO 0x2800
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/*
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* MAC registers.
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*/
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#define MAC_CONTROL 0x0000 /* MAC control */
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#define CONTROL_RA (1U << 31) /* receive all */
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#define CONTROL_EM (1U << 30) /* 1 = big endian */
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#define CONTROL_DO (1U << 23) /* disable receive own */
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#define CONTROL_LM(x) ((x) << 21) /* loopback mode */
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/* 0 = normal */
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/* 1 = internal loopback */
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/* 2 = external loopback */
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/* 3 = reserved */
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#define CONTROL_F (1U << 20) /* full-duplex mode */
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#define CONTROL_PM (1U << 19) /* pass all multicast */
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#define CONTROL_PR (1U << 18) /* promiscuous mode */
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#define CONTROL_IF (1U << 17) /* inverse filtering */
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#define CONTROL_PB (1U << 16) /* pass bad frames */
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#define CONTROL_HO (1U << 15) /* hash-only filtering */
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#define CONTROL_HP (1U << 13) /* hash-perfect filtering */
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#define CONTROL_LC (1U << 12) /* re-tx on late collision */
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#define CONTROL_DB (1U << 11) /* disable broadcast frames */
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#define CONTROL_DR (1U << 10) /* disable retry */
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#define CONTROL_AP (1U << 8) /* automatic pad stripping */
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#define CONTROL_BL(x) ((x) << 6) /* backoff limit */
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#define CONTROL_DC (1U << 5) /* deferral check */
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#define CONTROL_TE (1U << 3) /* transmitter enable */
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#define CONTROL_RE (1U << 2) /* receiver enable */
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#define MAC_ADDRHIGH 0x0004 /* high 16 bits of station address */
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#define MAC_ADDRLOW 0x0008 /* low 32 bits of station address */
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#define MAC_HASHHIGH 0x000c /* high 32 bits of multicast hash */
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#define MAC_HASHLOW 0x0010 /* low 32 bits of multicast hash */
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#define MAC_MIICTRL 0x0014 /* MII PHY control */
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#define MIICTRL_PHYADDR(x) ((x) << 11) /* PHY address */
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#define MIICTRL_MIIREG(x) ((x) << 6) /* MII register */
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#define MIICTRL_MW (1U << 1) /* MII write */
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#define MIICTRL_MB (1U << 0) /* MII busy */
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#define MAC_MIIDATA 0x0018 /* MII PHY data */
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#define MIIDATA_MASK 0xffff /* MII data bits */
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#define MAC_FLOWCTRL 0x001c /* control frame generation control */
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#define FLOWCTRL_PT(x) ((x) << 16) /* pause time */
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#define FLOWCTRL_PC (1U << 2) /* pass control frame */
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#define FLOWCTRL_FE (1U << 1) /* flow control enable */
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#define FLOWCTRL_FB (1U << 0) /* flow control busy */
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#define MAC_VLAN1 0x0020 /* VLAN1 tag */
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#define MAC_VLAN2 0x0024 /* VLAN2 tag */
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/*
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* MAC Enable registers.
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*/
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#define MACEN_JP (1U << 6) /* jumbo packet enable */
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#define MACEN_E2 (1U << 5) /* enable2 */
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#define MACEN_E1 (1U << 4) /* enable1 */
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#define MACEN_C (1U << 3) /* 0 == coherent */
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#define MACEN_TS (1U << 2) /* disable toss */
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#define MACEN_E0 (1U << 1) /* enable0 */
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#define MACEN_CE (1U << 0) /* clock enable */
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/*
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* MAC DMA registers.
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*/
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#define MACDMA_TX_ENTRY(x) ((x) << 4)
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#define MACDMA_RX_ENTRY(x) (((x) << 4) + 0x100)
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#define MACDMA_TX_STAT(x) (MACDMA_TX_ENTRY(x) + 0x00)
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#define MACDMA_TX_ADDR(x) (MACDMA_TX_ENTRY(x) + 0x04)
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#define MACDMA_TX_LEN(x) (MACDMA_TX_ENTRY(x) + 0x08)
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#define MACDMA_RX_STAT(x) (MACDMA_RX_ENTRY(x) + 0x00)
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#define MACDMA_RX_ADDR(x) (MACDMA_RX_ENTRY(x) + 0x04)
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#define RX_STAT_MI (1U << 31) /* missed frame */
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#define RX_STAT_PF (1U << 30) /* packet filter pass */
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#define RX_STAT_FF (1U << 29) /* filtering fail */
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#define RX_STAT_BF (1U << 28) /* broadcast frame */
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#define RX_STAT_MF (1U << 27) /* multicast frame */
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#define RX_STAT_UC (1U << 26) /* unsupported control frame */
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#define RX_STAT_CF (1U << 25) /* control frame */
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#define RX_STAT_LE (1U << 24) /* length error */
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#define RX_STAT_V2 (1U << 23) /* VLAN2 match */
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#define RX_STAT_V1 (1U << 22) /* VLAN1 match */
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#define RX_STAT_CR (1U << 21) /* CRC error */
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#define RX_STAT_DB (1U << 20) /* dribbling bit */
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#define RX_STAT_ME (1U << 19) /* MII error */
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#define RX_STAT_FT (1U << 18) /* 0 = 802.3, 1 = Ethernet */
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#define RX_STAT_CS (1U << 17) /* collision seen */
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#define RX_STAT_FL (1U << 16) /* frame too long */
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#define RX_STAT_RF (1U << 15) /* runt frame */
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#define RX_STAT_WT (1U << 14) /* watchdog timeout */
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#define RX_STAT_L(x) ((x) & 0x3fff) /* frame length */
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#define RX_STAT_ERRS (RX_STAT_MI | RX_STAT_UC | RX_STAT_LE | RX_STAT_CR | \
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RX_STAT_DB | RX_STAT_ME | RX_STAT_CS | RX_STAT_FL | \
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RX_STAT_RF | RX_STAT_WT)
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#define RX_ADDR_CB(x) (((x) >> 2) & 3)/* current buffer */
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#define RX_ADDR_DN (1U << 1) /* transaction done */
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#define RX_ADDR_EN (1U << 0) /* enable this buffer */
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#define TX_STAT_PR (1U << 31) /* packet retry */
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#define TX_STAT_CC(x) (((x) >> 10) & 0xf) /* collision count */
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#define TX_STAT_LO (1U << 9) /* late collision observed */
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#define TX_STAT_DF (1U << 8) /* deferred transmission */
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#define TX_STAT_UR (1U << 7) /* data underrun */
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#define TX_STAT_EC (1U << 6) /* excessive collisions */
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#define TX_STAT_LC (1U << 5) /* late collision */
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#define TX_STAT_ED (1U << 4) /* excessive deferral */
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#define TX_STAT_LS (1U << 3) /* loss of carrier */
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#define TX_STAT_NC (1U << 2) /* no carrier */
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#define TX_STAT_JT (1U << 1) /* jabber timeout */
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#define TX_STAT_FA (1U << 0) /* frame aborted */
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#define TX_ADDR_CB(x) (((x) >> 2) & 3)/* current buffer */
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#define TX_ADDR_DN (1U << 1) /* transaction done */
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#define TX_ADDR_EN (1U << 0) /* enable this buffer */
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#endif /* _MIPS_ALCHEMY_DEV_AUMACREG_H_ */
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