332 lines
9.6 KiB
C
332 lines
9.6 KiB
C
/* $NetBSD: if_dgereg.h,v 1.2 2005/12/11 12:22:49 christos Exp $ */
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/*
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* Copyright (c) 2004, SUNET, Swedish University Computer Network.
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* All rights reserved.
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*
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* Written by Anders Magnusson for SUNET, Swedish University Computer Network.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* SUNET, Swedish University Computer Network.
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* 4. The name of SUNET may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY SUNET ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/* PCI registers */
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#define DGE_PCI_BAR 0x10
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#define DGE_PCIX_CMD 0xe4
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/* PCIX CMD bits */
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#define PCIX_MMRBC_MSK 0x000c0000
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#define PCIX_MMRBC_512 0x00000000
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#define PCIX_MMRBC_1024 0x00040000
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#define PCIX_MMRBC_2048 0x00080000
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#define PCIX_MMRBC_4096 0x000c0000
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/* General registers */
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#define DGE_CTRL0 0x000
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#define DGE_CTRL1 0x008
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#define DGE_STATUS 0x010
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#define DGE_EECD 0x018
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#define DGE_MFS 0x020
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/* Interrupt control registers */
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#define DGE_ICR 0x080
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#define DGE_ICS 0x088
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#define DGE_IMS 0x090
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#define DGE_IMC 0x098
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/* Receiver control registers */
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#define DGE_RCTL 0x0100
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#define DGE_FCRTL 0x0108
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#define DGE_FCRTH 0x0110
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#define DGE_RDBAL 0x0118
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#define DGE_RDBAH 0x011c
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#define DGE_RDLEN 0x0120
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#define DGE_RDH 0x0128
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#define DGE_RDT 0x0130
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#define DGE_RDTR 0x0138
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#define DGE_RXDCTL 0x0140
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#define DGE_RAIDC 0x0148
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#define DGE_RXCSUM 0x0158
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#define DGE_RAL 0x0180
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#define DGE_RAH 0x0184
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#define DGE_MTA 0x0200
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/* Transmit control registers */
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#define DGE_TCTL 0x0600
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#define DGE_TDBAL 0x0608
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#define DGE_TDBAH 0x060c
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#define DGE_TDLEN 0x0610
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#define DGE_TDH 0x0618
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#define DGE_TDT 0x0620
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#define DGE_TIDV 0x0628
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#define DGE_TXDCTL 0x0630
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#define DGE_TSPMT 0x0638
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#define DGE_PAP 0x0640
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/* PHY communications */
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#define DGE_MDIO 0x0758
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#define DGE_MDIRW 0x0760
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/* Statistics */
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#define DGE_TPRL 0x2000
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#define DGE_TPRH 0x2004
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/*
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* CTRL0 bit definitions.
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*/
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#define CTRL0_LRST 0x00000008
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#define CTRL0_JFE 0x00000010
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#define CTRL0_XLE 0x00000020
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#define CTRL0_MDCS 0x00000040
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#define CTRL0_CMDC 0x00000080
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#define CTRL0_SDP0 0x00040000
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#define CTRL0_SDP1 0x00080000
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#define CTRL0_SDP2 0x00100000
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#define CTRL0_SDP3 0x00200000
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#define CTRL0_SDP0_DIR 0x00400000
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#define CTRL0_SDP1_DIR 0x00800000
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#define CTRL0_SDP2_DIR 0x01000000
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#define CTRL0_SDP3_DIR 0x02000000
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#define CTRL0_RST 0x04000000
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#define CTRL0_RPE 0x08000000
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#define CTRL0_TPE 0x10000000
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#define CTRL0_VME 0x40000000
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/*
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* CTRL1 bit definitions.
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*/
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#define CTRL1_EE_RST 0x00002000
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/*
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* STATUS bit definitions.
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*/
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#define STATUS_LINKUP 0x00000002
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#define STATUS_BUS64 0x00001000
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#define STATUS_PCIX 0x00002000
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#define STATUS_PCIX_MSK 0x0000C000
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#define STATUS_PCIX_66 0x00000000
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#define STATUS_PCIX_100 0x00004000
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#define STATUS_PCIX_133 0x00008000
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/*
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* Interrupt control registers bit definitions.
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*/
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#define ICR_TXDW 0x00000001
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#define ICR_TXQE 0x00000002
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#define ICR_LSC 0x00000004
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#define ICR_RXSEQ 0x00000008
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#define ICR_RXDMT0 0x00000010
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#define ICR_RXO 0x00000040
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#define ICR_RXT0 0x00000080
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#define ICR_GPI0 0x00000800
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#define ICR_GPI1 0x00001000
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#define ICR_GPI2 0x00002000
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#define ICR_GPI3 0x00004000
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/*
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* RCTL bit definitions.
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*/
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#define RCTL_RXEN 0x00000002
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#define RCTL_SBP 0x00000004
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#define RCTL_UPE 0x00000008
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#define RCTL_MPE 0x00000010
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#define RCTL_RDMTS_12 0x00000000
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#define RCTL_RDMTS_14 0x00000100
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#define RCTL_RDMTS_18 0x00000200
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#define RCTL_BAM 0x00008000
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#define RCTL_BSIZE_2k 0x00000000
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#define RCTL_BSIZE_4k 0x00010000
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#define RCTL_BSIZE_8k 0x00020000
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#define RCTL_BSIZE_16k 0x00030000
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#define RCTL_VFE 0x00040000
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#define RCTL_CFIEN 0x00080000
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#define RCTL_CFI 0x00100000
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#define RCTL_RPDA_MC 0x00400000
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#define RCTL_CFF 0x00800000
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#define RCTL_SECRC 0x04000000
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#define RCTL_MO(x) ((x) << 12)
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#define FCRTL_XONE 0x80000000
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/*
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* RXDCTL macros.
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*/
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#define RXDCTL_PTHRESH(x) (x)
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#define RXDCTL_HTHRESH(x) ((x) << 9)
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#define RXDCTL_WTHRESH(x) ((x) << 18)
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/*
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* RXCSUM bit definitions.
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*/
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#define RXCSUM_IPOFL 0x00000100
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#define RXCSUM_TUOFL 0x00000200
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/*
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* RAH/RAL macros.
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*/
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#define RAH_AV 0x80000000
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#define RA_TABSIZE 16 /* # of direct-filtered addresses */
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#define RA_ADDR(reg, idx) ((reg) + (idx) * 8)
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/*
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* MTA macros.
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*/
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#define MC_TABSIZE 128 /* Size of multicast array table */
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/*
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* TCTL bit definitions.
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*/
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#define TCTL_TCE 0x00000001
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#define TCTL_TXEN 0x00000002
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#define TCTL_TPDE 0x00000004
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/*
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* TXDCTL macros.
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*/
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#define TXDCTL_PTHRESH(x) (x)
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#define TXDCTL_HTHRESH(x) ((x) << 8)
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#define TXDCTL_WTHRESH(x) ((x) << 16)
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/*
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* MDIO communication bits.
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* This is for "New Protocol".
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*/
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#define MDIO_REG(x) ((x) & 0xffff)
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#define MDIO_DEV(x) ((x) << 16)
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#define MDIO_PHY(x) ((x) << 21)
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#define MDIO_ADDR 0
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#define MDIO_WRITE (1 << 26)
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#define MDIO_READ (1 << 27)
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#define MDIO_OLD_P (1 << 28)
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#define MDIO_CMD (1 << 30)
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/*
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* EEPROM stuff.
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* The 10GbE card uses an ATMEL AT93C46 in 64x16 mode,
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* see http://www.atmel.com/dyn/resources/prod_documents/doc0172.pdf
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*/
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/* EEPROM bit masks in the EECD register */
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#define EECD_SK 0x01
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#define EECD_CS 0x02
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#define EECD_DI 0x04
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#define EECD_DO 0x08
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#define EEPROM_SIZE 64 /* 64 word in length */
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#define EEPROM_CKSUM 0xbaba
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#define EE_ADDR01 0 /* Offset in EEPROM for MAC address 0-1 */
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#define EE_ADDR23 1 /* Offset in EEPROM for MAC address 2-3 */
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#define EE_ADDR45 2 /* Offset in EEPROM for MAC address 4-5 */
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/*
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* Transmit descriptor definitions.
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*/
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struct dge_tdes {
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uint32_t dt_baddrl; /* Lower 32 bits of buffer address */
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uint32_t dt_baddrh; /* Upper 32 bits of buffer address */
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uint32_t dt_ctl; /* Command/Type/Length */
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uint8_t dt_status; /* Transmitted data status info */
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uint8_t dt_popts; /* Packet options */
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uint16_t dt_vlan; /* VLAN information */
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} __attribute__((__packed__));
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/*
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* Context transmit descriptor, "overlayed" on the above struct.
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*/
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struct dge_ctdes {
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#if 0
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uint8_t dc_ipcss; /* IP checksum start */
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uint8_t dc_ipcso; /* IP checksum offset */
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uint16_t dc_ipcse; /* IP checksum ending */
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uint8_t dc_tucss; /* TCP/UDP checksum start */
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uint8_t dc_tucso; /* TCP/UDP checksum offset */
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uint16_t dc_tucse; /* TCP/UDP checksum ending */
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uint32_t dc_ctl; /* Command/Type/Length (as above) */
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uint8_t dc_status; /* Status info (as above) */
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uint8_t dc_hdrlen; /* Header length */
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uint16_t dc_mss; /* Maximum segment size */
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#else
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uint32_t dc_tcpip_ipcs; /* IP checksum context */
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uint32_t dc_tcpip_tucs; /* TCP/UDP checksum context */
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uint32_t dc_tcpip_cmdlen;
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uint32_t dc_tcpip_seg; /* TCP segmentation context */
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#endif
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} __attribute__((__packed__));
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#define TDESC_DTYP_CTD 0x00000000
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#define TDESC_DTYP_DATA 0x00100000
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#define TDESC_DCMD_IDE 0x80000000
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#define TDESC_DCMD_VLE 0x40000000
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#define TDESC_DCMD_RS 0x08000000
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#define TDESC_DCMD_TSE 0x04000000
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#define TDESC_DCMD_EOP 0x01000000
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#define TDESC_TUCMD_IDE 0x80000000
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#define TDESC_TUCMD_RS 0x08000000
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#define TDESC_TUCMD_TSE 0x04000000
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#define TDESC_TUCMD_IP 0x02000000
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#define TDESC_TUCMD_TCP 0x01000000
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#define DGE_TCPIP_IPCSS(x) (x)
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#define DGE_TCPIP_IPCSO(x) ((x) << 8)
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#define DGE_TCPIP_IPCSE(x) ((x) << 16)
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#define DGE_TCPIP_TUCSS(x) (x)
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#define DGE_TCPIP_TUCSO(x) ((x) << 8)
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#define DGE_TCPIP_TUCSE(x) ((x) << 16)
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#define TDESC_STA_DD 0x01
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#define TDESC_POPTS_TXSM 0x02
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#define TDESC_POPTS_IXSM 0x01
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/*
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* Receive descriptor definitions.
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*/
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struct dge_rdes {
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uint32_t dr_baddrl; /* Lower 32 bits of buffer address */
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uint32_t dr_baddrh; /* Upper 32 bits of buffer address */
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uint16_t dr_len; /* Length of receive packet */
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uint16_t dr_cksum; /* Packet checksum */
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uint8_t dr_status; /* Received data status info */
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uint8_t dr_errors; /* Receive errors */
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uint16_t dr_special; /* VLAN (802.1q) information */
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} __attribute__((__packed__));
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#define RDESC_STS_PIF 0x80 /* Exact filter match */
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#define RDESC_STS_IPCS 0x40 /* IP Checksum calculated */
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#define RDESC_STS_TCPCS 0x20 /* TCP checksum calculated */
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#define RDESC_STS_VP 0x08 /* Packet is 802.1q */
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#define RDESC_STS_IXSM 0x04 /* Ignore checksum */
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#define RDESC_STS_EOP 0x02 /* End of packet */
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#define RDESC_STS_DD 0x01 /* Descriptor done */
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#define RDESC_ERR_RXE 0x80 /* RX data error */
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#define RDESC_ERR_IPE 0x40 /* IP checksum error */
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#define RDESC_ERR_TCPE 0x20 /* TCP/UDP checksum error */
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#define RDESC_ERR_P 0x08 /* Parity error */
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#define RDESC_ERR_SE 0x02 /* Symbol error */
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#define RDESC_ERR_CE 0x01 /* CRC/Alignment error */
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