585dd234ff
properties (similar to what the "dsrtc" driver does), and provide DT compat strings corresponding to those models. Allow config flags to specify the model for non-FDT platforms (also like "dsrtc").
536 lines
14 KiB
C
536 lines
14 KiB
C
/* $NetBSD: m41st84.c,v 1.27 2020/01/03 03:44:42 thorpej Exp $ */
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/*
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* Copyright (c) 2003 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Steve C. Woodford and Jason R. Thorpe for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: m41st84.c,v 1.27 2020/01/03 03:44:42 thorpej Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <sys/kernel.h>
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#include <sys/fcntl.h>
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#include <sys/uio.h>
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#include <sys/conf.h>
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#include <sys/event.h>
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#include <dev/clock_subr.h>
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#include <dev/i2c/i2cvar.h>
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#include <dev/i2c/m41st84reg.h>
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#include <dev/i2c/m41st84var.h>
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#include "ioconf.h"
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struct strtc_model {
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uint16_t sm_model;
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uint8_t sm_nvram_start;
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uint8_t sm_nvram_size;
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uint32_t sm_flags;
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};
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#define STRTC_F_HAS_WDOG __BIT(0)
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static const struct strtc_model m41t80_model = {
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.sm_model = 80,
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};
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static const struct strtc_model m41t81_model = {
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.sm_model = 81,
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.sm_flags = STRTC_F_HAS_WDOG,
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};
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static const struct strtc_model m48t84_model = {
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.sm_model = 84,
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.sm_nvram_start = M41ST84_USER_RAM,
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.sm_nvram_size = M41ST84_USER_RAM_SIZE,
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.sm_flags = STRTC_F_HAS_WDOG,
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};
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static const struct device_compatible_entry compat_data[] = {
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{ "st,m41t80", (uintptr_t)&m41t80_model },
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{ "st,m41t81", (uintptr_t)&m41t81_model },
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{ "st,m41t84", (uintptr_t)&m48t84_model },
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{ NULL, 0 },
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};
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struct strtc_softc {
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device_t sc_dev;
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i2c_tag_t sc_tag;
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int sc_address;
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int sc_open;
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const struct strtc_model *sc_model;
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struct todr_chip_handle sc_todr;
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};
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static void strtc_attach(device_t, device_t, void *);
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static int strtc_match(device_t, cfdata_t, void *);
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CFATTACH_DECL_NEW(strtc, sizeof(struct strtc_softc),
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strtc_match, strtc_attach, NULL, NULL);
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dev_type_open(strtc_open);
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dev_type_close(strtc_close);
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dev_type_read(strtc_read);
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dev_type_write(strtc_write);
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const struct cdevsw strtc_cdevsw = {
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.d_open = strtc_open,
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.d_close = strtc_close,
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.d_read = strtc_read,
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.d_write = strtc_write,
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.d_ioctl = noioctl,
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.d_stop = nostop,
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.d_tty = notty,
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.d_poll = nopoll,
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.d_mmap = nommap,
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.d_kqfilter = nokqfilter,
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.d_discard = nodiscard,
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.d_flag = D_OTHER
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};
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static int strtc_clock_read(struct strtc_softc *sc, struct clock_ymdhms *);
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static int strtc_gettime_ymdhms(struct todr_chip_handle *,
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struct clock_ymdhms *);
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static int strtc_settime_ymdhms(struct todr_chip_handle *,
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struct clock_ymdhms *);
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static const struct strtc_model *
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strtc_model_by_number(u_int model)
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{
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const struct device_compatible_entry *dce;
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const struct strtc_model *sm;
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/* no model given; assume it's a 41T80 */
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if (model == 0)
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return &m41t80_model;
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for (dce = compat_data; dce->compat != NULL; dce++) {
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sm = (void *)dce->data;
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if (sm->sm_model == model)
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return sm;
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}
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return NULL;
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}
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static const struct strtc_model *
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strtc_model_by_compat(const struct i2c_attach_args *ia)
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{
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const struct device_compatible_entry *dce;
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const struct strtc_model *sm = NULL;
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if (iic_compatible_match(ia, compat_data, &dce))
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sm = (void *)dce->data;
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return sm;
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}
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static int
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strtc_match(device_t parent, cfdata_t cf, void *arg)
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{
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struct i2c_attach_args *ia = arg;
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int match_result;
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if (iic_use_direct_match(ia, cf, compat_data, &match_result))
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return match_result;
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if (strtc_model_by_number(cf->cf_flags & 0xffff) == NULL)
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return 0;
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/* indirect config - check typical address */
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if (ia->ia_addr == M41ST84_ADDR)
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return I2C_MATCH_ADDRESS_ONLY;
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return 0;
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}
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static void
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strtc_attach(device_t parent, device_t self, void *arg)
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{
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struct strtc_softc *sc = device_private(self);
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struct i2c_attach_args *ia = arg;
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const struct strtc_model *sm;
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if ((sm = strtc_model_by_compat(ia)) == NULL)
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sm = strtc_model_by_number(device_cfdata(self)->cf_flags);
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if (sm == NULL) {
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aprint_error(": unable to determine model!\n");
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return;
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}
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aprint_naive(": Real-time Clock%s\n",
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sm->sm_nvram_size ? "/NVRAM" : "");
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aprint_normal(": M41T%d Real-time Clock%s", sm->sm_model,
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sm->sm_nvram_size ? "/NVRAM" : "");
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sc->sc_tag = ia->ia_tag;
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sc->sc_address = ia->ia_addr;
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sc->sc_model = sm;
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sc->sc_dev = self;
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sc->sc_open = 0;
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sc->sc_todr.cookie = sc;
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sc->sc_todr.todr_gettime = NULL;
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sc->sc_todr.todr_settime = NULL;
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sc->sc_todr.todr_gettime_ymdhms = strtc_gettime_ymdhms;
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sc->sc_todr.todr_settime_ymdhms = strtc_settime_ymdhms;
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sc->sc_todr.todr_setwen = NULL;
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todr_attach(&sc->sc_todr);
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}
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/*ARGSUSED*/
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int
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strtc_open(dev_t dev, int flag, int fmt, struct lwp *l)
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{
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struct strtc_softc *sc;
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if ((sc = device_lookup_private(&strtc_cd, minor(dev))) == NULL)
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return (ENXIO);
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/* XXX: Locking */
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if (sc->sc_open)
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return (EBUSY);
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sc->sc_open = 1;
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return (0);
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}
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/*ARGSUSED*/
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int
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strtc_close(dev_t dev, int flag, int fmt, struct lwp *l)
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{
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struct strtc_softc *sc;
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if ((sc = device_lookup_private(&strtc_cd, minor(dev))) == NULL)
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return (ENXIO);
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sc->sc_open = 0;
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return (0);
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}
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/*ARGSUSED*/
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int
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strtc_read(dev_t dev, struct uio *uio, int flags)
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{
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struct strtc_softc *sc;
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u_int8_t ch, cmdbuf[1];
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int a, error;
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if ((sc = device_lookup_private(&strtc_cd, minor(dev))) == NULL)
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return (ENXIO);
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const struct strtc_model * const sm = sc->sc_model;
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if (uio->uio_offset >= sm->sm_nvram_size)
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return (EINVAL);
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if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0)
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return (error);
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while (uio->uio_resid && uio->uio_offset < sm->sm_nvram_size) {
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a = (int)uio->uio_offset;
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cmdbuf[0] = a + sm->sm_nvram_start;
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if ((error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP,
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sc->sc_address, cmdbuf, 1,
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&ch, 1, 0)) != 0) {
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iic_release_bus(sc->sc_tag, 0);
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aprint_error_dev(sc->sc_dev,
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"strtc_read: read failed at 0x%x\n", a);
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return (error);
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}
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if ((error = uiomove(&ch, 1, uio)) != 0) {
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iic_release_bus(sc->sc_tag, 0);
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return (error);
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}
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}
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iic_release_bus(sc->sc_tag, 0);
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return (0);
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}
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/*ARGSUSED*/
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int
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strtc_write(dev_t dev, struct uio *uio, int flags)
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{
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struct strtc_softc *sc;
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u_int8_t cmdbuf[2];
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int a, error;
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if ((sc = device_lookup_private(&strtc_cd, minor(dev))) == NULL)
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return (ENXIO);
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const struct strtc_model * const sm = sc->sc_model;
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if (uio->uio_offset >= sm->sm_nvram_size)
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return (EINVAL);
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if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0)
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return (error);
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while (uio->uio_resid && uio->uio_offset < sm->sm_nvram_size) {
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a = (int)uio->uio_offset;
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cmdbuf[0] = a + sm->sm_nvram_start;
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if ((error = uiomove(&cmdbuf[1], 1, uio)) != 0)
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break;
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if ((error = iic_exec(sc->sc_tag,
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uio->uio_resid ? I2C_OP_WRITE : I2C_OP_WRITE_WITH_STOP,
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sc->sc_address, cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) {
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aprint_error_dev(sc->sc_dev,
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"strtc_write: write failed at 0x%x\n", a);
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break;
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}
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}
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iic_release_bus(sc->sc_tag, 0);
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return (error);
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}
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static int
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strtc_gettime_ymdhms(struct todr_chip_handle *ch, struct clock_ymdhms *dt)
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{
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struct strtc_softc *sc = ch->cookie;
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struct clock_ymdhms check;
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int retries, error;
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memset(dt, 0, sizeof(*dt));
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memset(&check, 0, sizeof(check));
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/*
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* Since we don't support Burst Read, we have to read the clock twice
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* until we get two consecutive identical results.
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*/
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retries = 5;
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do {
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if ((error = strtc_clock_read(sc, dt)) == 0)
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error = strtc_clock_read(sc, &check);
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if (error)
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return error;
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} while (memcmp(dt, &check, sizeof(check)) != 0 && --retries);
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return (0);
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}
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static int
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strtc_clock_read(struct strtc_softc *sc, struct clock_ymdhms *dt)
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{
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u_int8_t bcd[M41ST84_REG_DATE_BYTES], cmdbuf[2];
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int i, error;
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if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) {
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aprint_error_dev(sc->sc_dev,
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"strtc_clock_read: failed to acquire I2C bus\n");
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return (error);
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}
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/*
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* Check for the HT bit -- if set, then clock lost power & stopped
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* If that happened, then clear the bit so that the clock will have
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* a chance to run again.
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*/
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cmdbuf[0] = M41ST84_REG_AL_HOUR;
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if ((error = iic_exec(sc->sc_tag, I2C_OP_READ, sc->sc_address,
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cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) {
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iic_release_bus(sc->sc_tag, 0);
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aprint_error_dev(sc->sc_dev,
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"strtc_clock_read: failed to read HT\n");
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return (error);
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}
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if (cmdbuf[1] & M41ST84_AL_HOUR_HT) {
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cmdbuf[1] &= ~M41ST84_AL_HOUR_HT;
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if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address,
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cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) {
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iic_release_bus(sc->sc_tag, 0);
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aprint_error_dev(sc->sc_dev,
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"strtc_clock_read: failed to reset HT\n");
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return (error);
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}
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}
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/* Read each RTC register in order. */
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for (i = M41ST84_REG_CSEC; i < M41ST84_REG_DATE_BYTES; i++) {
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cmdbuf[0] = i;
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if ((error = iic_exec(sc->sc_tag, I2C_OP_READ_WITH_STOP,
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sc->sc_address, cmdbuf, 1,
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&bcd[i], 1, 0)) != 0) {
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iic_release_bus(sc->sc_tag, 0);
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aprint_error_dev(sc->sc_dev,
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"strtc_clock_read: failed to read rtc "
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"at 0x%x\n", i);
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return (error);
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}
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}
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/* Done with I2C */
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iic_release_bus(sc->sc_tag, 0);
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/*
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* Convert the M41ST84's register values into something useable
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*/
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dt->dt_sec = bcdtobin(bcd[M41ST84_REG_SEC] & M41ST84_SEC_MASK);
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dt->dt_min = bcdtobin(bcd[M41ST84_REG_MIN] & M41ST84_MIN_MASK);
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dt->dt_hour = bcdtobin(bcd[M41ST84_REG_CENHR] & M41ST84_HOUR_MASK);
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dt->dt_day = bcdtobin(bcd[M41ST84_REG_DATE] & M41ST84_DATE_MASK);
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dt->dt_mon = bcdtobin(bcd[M41ST84_REG_MONTH] & M41ST84_MONTH_MASK);
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/* XXX: Should be an MD way to specify EPOCH used by BIOS/Firmware */
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/* XXX: Wait, isn't that what rtc_offset in todr_gettime() is for? */
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dt->dt_year = bcdtobin(bcd[M41ST84_REG_YEAR]) + POSIX_BASE_YEAR;
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return (0);
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}
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static int
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strtc_settime_ymdhms(struct todr_chip_handle *ch, struct clock_ymdhms *dt)
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{
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struct strtc_softc *sc = ch->cookie;
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uint8_t bcd[M41ST84_REG_DATE_BYTES], cmdbuf[2];
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int i, error;
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/*
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* Convert our time representation into something the M41ST84
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* can understand.
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*/
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bcd[M41ST84_REG_CSEC] = bintobcd(0); /* must always write as 0 */
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bcd[M41ST84_REG_SEC] = bintobcd(dt->dt_sec);
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bcd[M41ST84_REG_MIN] = bintobcd(dt->dt_min);
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bcd[M41ST84_REG_CENHR] = bintobcd(dt->dt_hour);
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bcd[M41ST84_REG_DATE] = bintobcd(dt->dt_day);
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bcd[M41ST84_REG_DAY] = bintobcd(dt->dt_wday);
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bcd[M41ST84_REG_MONTH] = bintobcd(dt->dt_mon);
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bcd[M41ST84_REG_YEAR] = bintobcd((dt->dt_year - POSIX_BASE_YEAR) % 100);
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if ((error = iic_acquire_bus(sc->sc_tag, 0)) != 0) {
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aprint_error_dev(sc->sc_dev,
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"strtc_clock_write: failed to acquire I2C bus\n");
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return (error);
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}
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/* Stop the clock */
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cmdbuf[0] = M41ST84_REG_SEC;
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cmdbuf[1] = M41ST84_SEC_ST;
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if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address,
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cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) {
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iic_release_bus(sc->sc_tag, 0);
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aprint_error_dev(sc->sc_dev,
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"strtc_clock_write: failed to Hold Clock\n");
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return (error);
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}
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/*
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* Check for the HT bit -- if set, then clock lost power & stopped
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* If that happened, then clear the bit so that the clock will have
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* a chance to run again.
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*/
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cmdbuf[0] = M41ST84_REG_AL_HOUR;
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if ((error = iic_exec(sc->sc_tag, I2C_OP_READ, sc->sc_address,
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cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) {
|
|
iic_release_bus(sc->sc_tag, 0);
|
|
aprint_error_dev(sc->sc_dev,
|
|
"strtc_clock_write: failed to read HT\n");
|
|
return (error);
|
|
}
|
|
if (cmdbuf[1] & M41ST84_AL_HOUR_HT) {
|
|
cmdbuf[1] &= ~M41ST84_AL_HOUR_HT;
|
|
if ((error = iic_exec(sc->sc_tag, I2C_OP_WRITE, sc->sc_address,
|
|
cmdbuf, 1, &cmdbuf[1], 1, 0)) != 0) {
|
|
iic_release_bus(sc->sc_tag, 0);
|
|
aprint_error_dev(sc->sc_dev,
|
|
"strtc_clock_write: failed to reset HT\n");
|
|
return (error);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Write registers in reverse order. The last write (to the Seconds
|
|
* register) will undo the Clock Hold, above.
|
|
*/
|
|
for (i = M41ST84_REG_DATE_BYTES - 1; i >= 0; i--) {
|
|
cmdbuf[0] = i;
|
|
if ((error = iic_exec(sc->sc_tag,
|
|
i ? I2C_OP_WRITE : I2C_OP_WRITE_WITH_STOP,
|
|
sc->sc_address, cmdbuf, 1, &bcd[i], 1, 0)) != 0) {
|
|
iic_release_bus(sc->sc_tag, 0);
|
|
aprint_error_dev(sc->sc_dev,
|
|
"strtc_clock_write: failed to write rtc "
|
|
" at 0x%x\n", i);
|
|
/* XXX: Clock Hold is likely still asserted! */
|
|
return (error);
|
|
}
|
|
}
|
|
|
|
iic_release_bus(sc->sc_tag, 0);
|
|
|
|
return (0);
|
|
}
|
|
|
|
void
|
|
strtc_wdog_config(void *arg, uint8_t wd)
|
|
{
|
|
struct strtc_softc *sc = arg;
|
|
uint8_t cmdbuf[2];
|
|
|
|
if ((sc->sc_model->sm_flags & STRTC_F_HAS_WDOG) == 0) {
|
|
aprint_error_dev(sc->sc_dev,
|
|
"strtc_wdog_config: watchdog timer not present\n");
|
|
return;
|
|
}
|
|
|
|
if (iic_acquire_bus(sc->sc_tag, 0)) {
|
|
aprint_error_dev(sc->sc_dev,
|
|
"strtc_wdog_config: failed to acquire I2C bus\n");
|
|
return;
|
|
}
|
|
|
|
cmdbuf[0] = M41ST84_REG_WATCHDOG;
|
|
cmdbuf[1] = wd;
|
|
|
|
if (iic_exec(sc->sc_tag, I2C_OP_WRITE_WITH_STOP, sc->sc_address,
|
|
cmdbuf, 1, &cmdbuf[1], 1, 0)) {
|
|
aprint_error_dev(sc->sc_dev,
|
|
"strtc_wdog_config: failed to write watchdog\n");
|
|
return;
|
|
}
|
|
|
|
iic_release_bus(sc->sc_tag, 0);
|
|
}
|