120 lines
4.6 KiB
C
120 lines
4.6 KiB
C
/* $NetBSD: hpcvar.h,v 1.7 2003/12/29 06:33:57 sekiya Exp $ */
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/*
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* Copyright (c) 2001 Rafal K. Boni
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ARCH_SGIMIPS_HPC_HPCVAR_H_
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#define _ARCH_SGIMIPS_HPC_HPCVAR_H_
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#define HPCDEV_IP12 (1U << 0) /* Indigo R3k, 4D/3x */
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#define HPCDEV_IP20 (1U << 1) /* Indigo R4k */
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#define HPCDEV_IP22 (1U << 2) /* Indigo2 */
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#define HPCDEV_IP24 (1U << 3) /* Indy */
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/* HPC 1.5/3 differ a bit, thus we need an abstraction layer */
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struct hpc_values {
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int revision;
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u_int32_t scsi0_regs;
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u_int32_t scsi0_regs_size;
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u_int32_t scsi0_cbp;
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u_int32_t scsi0_ndbp;
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u_int32_t scsi0_bc;
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u_int32_t scsi0_ctl;
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u_int32_t scsi0_gio;
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u_int32_t scsi0_dev;
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u_int32_t scsi0_dmacfg;
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u_int32_t scsi0_piocfg;
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u_int32_t scsi1_regs;
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u_int32_t scsi1_regs_size;
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u_int32_t scsi1_cbp;
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u_int32_t scsi1_ndbp;
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u_int32_t scsi1_bc;
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u_int32_t scsi1_ctl;
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u_int32_t scsi1_gio;
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u_int32_t scsi1_dev;
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u_int32_t scsi1_dmacfg;
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u_int32_t scsi1_piocfg;
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u_int32_t dmactl_dir;
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u_int32_t dmactl_flush;
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u_int32_t dmactl_active;
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u_int32_t dmactl_reset;
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u_int32_t enet_regs;
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u_int32_t enet_regs_size;
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u_int32_t enet_intdelay;
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u_int32_t enet_intdelayval;
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u_int32_t enetr_cbp;
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u_int32_t enetr_ndbp;
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u_int32_t enetr_bc;
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u_int32_t enetr_ctl;
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u_int32_t enetr_ctl_active;
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u_int32_t enetr_reset;
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u_int32_t enetr_dmacfg;
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u_int32_t enetr_piocfg;
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u_int32_t enetx_cbp;
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u_int32_t enetx_ndbp;
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u_int32_t enetx_bc;
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u_int32_t enetx_ctl;
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u_int32_t enetx_ctl_active;
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u_int32_t enetx_dev;
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u_int32_t enetr_fifo;
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u_int32_t enetr_fifo_size;
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u_int32_t enetx_fifo;
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u_int32_t enetx_fifo_size;
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u_int32_t scsi0_devregs_size;
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u_int32_t scsi1_devregs_size;
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u_int32_t enet_devregs;
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u_int32_t enet_devregs_size;
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u_int32_t pbus_fifo;
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u_int32_t pbus_fifo_size;
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u_int32_t pbus_bbram;
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u_int32_t scsi_max_xfer;
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u_int32_t scsi_dma_segs;
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u_int32_t scsi_dma_segs_size;
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u_int32_t clk_freq;
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u_int32_t dma_datain_cmd;
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u_int32_t dma_dataout_cmd;
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u_int32_t scsi_dmactl_flush;
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u_int32_t scsi_dmactl_active;
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u_int32_t scsi_dmactl_reset;
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};
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struct hpc_attach_args {
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const char *ha_name; /* name of device */
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bus_addr_t ha_devoff; /* offset of device */
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bus_addr_t ha_dmaoff; /* offset of DMA regs */
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int ha_irq; /* interrupt line */
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bus_space_tag_t ha_st; /* HPC space tag */
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bus_space_handle_t ha_sh; /* HPC space handle XXX */
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bus_dma_tag_t ha_dmat; /* HPC DMA tag */
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struct hpc_values *hpc_regs; /* HPC register definitions */
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};
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#endif /* _ARCH_SGIMIPS_HPC_HPCVAR_H_ */
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