284 lines
7.2 KiB
C
284 lines
7.2 KiB
C
/* $NetBSD: pci_machdep.c,v 1.10 2003/11/07 17:12:56 augustss Exp $ */
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/*
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* Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
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* Copyright (c) 1994 Charles M. Hannum. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Charles M. Hannum.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Machine-specific functions for PCI autoconfiguration.
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*
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* On PCs, there are two methods of generating PCI configuration cycles.
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* We try to detect the appropriate mechanism for this machine and set
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* up a few function pointers to access the correct method directly.
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*
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* The configuration method can be hard-coded in the config file by
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* using `options PCI_CONF_MODE=N', where `N' is the configuration mode
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* as defined section 3.6.4.1, `Generating Configuration Cycles'.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.10 2003/11/07 17:12:56 augustss Exp $");
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#include <sys/types.h>
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#include <sys/param.h>
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#include <sys/device.h>
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#include <sys/errno.h>
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#include <sys/extent.h>
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#include <sys/malloc.h>
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#include <sys/queue.h>
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#include <sys/systm.h>
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#include <sys/time.h>
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#include <machine/pcb.h>
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#include <uvm/uvm.h>
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#define _POWERPC_BUS_DMA_PRIVATE
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#include <machine/bus.h>
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#include <machine/pio.h>
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#include <machine/intr.h>
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#include <dev/ic/cpc700reg.h>
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#include <machine/pmppc.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pciconf.h>
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/*
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* Address conversion as seen from a PCI master.
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* XXX Shouldn't use 0x80000000, the actual value
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* should come from the BAR.
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*/
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#define PHYS_TO_PCI_MEM(x) ((x) + 0x80000000)
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#define PCI_MEM_TO_PHYS(x) ((x) - 0x80000000)
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static bus_addr_t phys_to_pci(bus_dma_tag_t, bus_addr_t);
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static bus_addr_t pci_to_phys(bus_dma_tag_t, bus_addr_t);
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struct powerpc_bus_dma_tag pci_bus_dma_tag = {
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0, /* _bounce_thresh */
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_bus_dmamap_create,
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_bus_dmamap_destroy,
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_bus_dmamap_load,
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_bus_dmamap_load_mbuf,
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_bus_dmamap_load_uio,
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_bus_dmamap_load_raw,
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_bus_dmamap_unload,
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NULL, /* _dmamap_sync */
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_bus_dmamem_alloc,
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_bus_dmamem_free,
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_bus_dmamem_map,
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_bus_dmamem_unmap,
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_bus_dmamem_mmap,
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phys_to_pci,
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pci_to_phys,
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};
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static bus_addr_t
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phys_to_pci(bus_dma_tag_t t, bus_addr_t a)
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{
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return PHYS_TO_PCI_MEM(a);
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}
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static bus_addr_t pci_to_phys(bus_dma_tag_t t, bus_addr_t a)
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{
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return PCI_MEM_TO_PHYS(a);
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}
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void
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pci_attach_hook(struct device *parent, struct device *self,
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struct pcibus_attach_args *pba)
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{
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}
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int
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pci_bus_maxdevs(pci_chipset_tag_t pc, int busno)
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{
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/*
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* Bus number is irrelevant. Configuration Mechanism 1 is in
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* use, can have devices 0-32 (i.e. the `normal' range).
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*/
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return (32);
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}
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pcitag_t
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pci_make_tag(pci_chipset_tag_t pc, int bus, int device, int function)
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{
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pcitag_t tag;
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if (bus >= 256 || device >= 32 || function >= 8)
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panic("pci_make_tag: bad request");
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tag = CPC_PCI_CONFIG_ENABLE |
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(bus << 16) | (device << 11) | (function << 8);
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return (tag);
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}
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void
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pci_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag, int *bp, int *dp, int *fp)
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{
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if (bp != NULL)
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*bp = (tag >> 16) & 0xff;
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if (dp != NULL)
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*dp = (tag >> 11) & 0x1f;
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if (fp != NULL)
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*fp = (tag >> 8) & 0x7;
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}
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#define SP_PCI(tag, reg) ((tag) | (reg))
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pcireg_t
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pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg)
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{
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pcireg_t data;
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struct faultbuf env, *oldfault;
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oldfault = curpcb->pcb_onfault;
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if (setfault(&env)) {
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curpcb->pcb_onfault = oldfault;
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return 0;
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}
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/*printf("pci_conf_read %x %x\n", tag, reg);*/
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out32rb(CPC_PCICFGADR, SP_PCI(tag, reg));
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data = in32rb(CPC_PCICFGDATA);
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/*out32rb(CPC_PCICFGADR, 0);*/
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curpcb->pcb_onfault = oldfault;
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return data;
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}
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void
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pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data)
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{
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struct faultbuf env, *oldfault;
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oldfault = curpcb->pcb_onfault;
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if (setfault(&env)) {
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curpcb->pcb_onfault = oldfault;
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return;
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}
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/*printf("pci_conf_write %x %x %x\n", tag, reg, data);*/
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out32rb(CPC_PCICFGADR, SP_PCI(tag, reg));
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out32rb(CPC_PCICFGDATA, data);
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/*out32rb(CPC_PCICFGADR, 0);*/
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curpcb->pcb_onfault = oldfault;
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}
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int
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pci_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp)
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{
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int pin = pa->pa_intrpin;
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int line = pa->pa_intrline;
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if (pin == 0) {
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/* No IRQ used. */
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goto bad;
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}
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if (pin > 4) {
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printf("pci_intr_map: bad interrupt pin %d\n", pin);
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goto bad;
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}
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if (line == 255) {
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printf("pci_intr_map: no mapping for pin %c\n", '@' + pin);
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goto bad;
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}
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/*printf("pci_intr_map pin=%d line=%d\n", pin, line);*/
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switch (line & 3) { /* XXX what should this be? */
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case 0: *ihp = PMPPC_I_BPMC_INTA; break;
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case 1: *ihp = PMPPC_I_BPMC_INTB; break;
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case 2: *ihp = PMPPC_I_BPMC_INTC; break;
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case 3: *ihp = PMPPC_I_BPMC_INTD; break;
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}
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return 0;
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bad:
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*ihp = -1;
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return 1;
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}
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const char *
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pci_intr_string(pci_chipset_tag_t pc, pci_intr_handle_t ih)
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{
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static char irqstr[8]; /* 4 + 2 + NULL + sanity */
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if (ih < 0 || ih >= ICU_LEN)
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panic("pci_intr_string: bogus handle 0x%x", ih);
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sprintf(irqstr, "irq %d", ih);
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return (irqstr);
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}
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const struct evcnt *
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pci_intr_evcnt(pci_chipset_tag_t pc, pci_intr_handle_t ih)
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{
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/* XXX for now, no evcnt parent reported */
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return NULL;
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}
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void *
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pci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih, int level,
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int (*func)(void *), void *arg)
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{
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/*
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* ih is the value assigned in pci_intr_map(), above.
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*/
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return intr_establish(ih, IST_LEVEL, level, func, arg);
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}
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void
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pci_intr_disestablish(pci_chipset_tag_t pc, void *cookie)
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{
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intr_disestablish(cookie);
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}
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void
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pci_conf_interrupt(pci_chipset_tag_t pc, int bus, int dev, int pin, int swiz,
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int *iline)
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{
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int line;
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line = (swiz + dev) & 3;
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/* XXX UGLY UGLY, figure out the real interrupt mapping */
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if (bus==3&&dev==2&&pin==1&&swiz==3) line=2;
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/*
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printf("pci_conf_interrupt: bus=%d dev=%d pin=%d swiz=%d => line=%d\n",
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bus, dev, pin, swiz, line);
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*/
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*iline = line;
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}
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