283b08193e
is leftover from whe we were loading at 0x10200000. if slave CPU uses this, he will paste his temporary L1 table in to the master's data. bad slave!
402 lines
12 KiB
ArmAsm
402 lines
12 KiB
ArmAsm
/* $NetBSD: gemini_start.S,v 1.4 2008/11/11 06:39:00 cliff Exp $ */
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/*
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* Machine dependant startup code for GEMINI boards.
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* Based on omap_start.S
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*
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* Copyright (c) 2002, 2003 Genetec Corporation. All rights reserved.
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* Written by Hiroyuki Bessho for Genetec Corporation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of Genetec Corporation may not be used to endorse or
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* promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* Copyright (c) 2003
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* Ichiro FUKUHARA <ichiro@ichiro.org>.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Ichiro FUKUHARA.
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* 4. The name of the company nor the name of the author may be used to
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* endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* Copyright (c) 2007 Microsoft
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Microsoft
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTERS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include "opt_gemini.h"
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#include "opt_com.h"
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#include "assym.h"
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#include <machine/asm.h>
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#include <arm/armreg.h>
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#undef DOMAIN_CLIENT /* assym.h defines as 1, but pte.h defines as 0x01 */
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#include <arm/arm32/pmap.h>
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#include <arm/gemini/gemini_reg.h>
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#include <evbarm/gemini/gemini.h>
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RCSID("$NetBSD: gemini_start.S,v 1.4 2008/11/11 06:39:00 cliff Exp $")
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#if defined(VERBOSE_INIT_ARM)
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# define _PUTCHAR(addr, areg, breg, c) \
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ldr areg, addr; \
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1: \
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ldr breg, [ areg, #0x14 ]; /* LSR */ \
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tst breg, #0x20; /* TXRDY? */ \
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beq 1b; \
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mov breg, #(c); /* c */ \
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str breg, [ areg ]; /* TXDATA */ \
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2: \
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ldr breg, [ areg, #0x14 ]; /* LSR */ \
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tst breg, #0x40; /* TSRE? */ \
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beq 2b;
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#else
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# define _PUTCHAR(addr, areg, breg, c)
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#endif
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/*
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* Kernel start routine for GEMINI Eval board.
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* At this point, this code has been loaded into SDRAM
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* and the MMU is off
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*/
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.section .start,"ax",%progbits
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.global _C_LABEL(gemini_start)
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_C_LABEL(gemini_start):
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/* Move into supervisor mode and disable IRQs/FIQs. */
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mrs r0, cpsr
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bic r0, r0, #PSR_MODE
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orr r0, r0, #(I32_bit | F32_bit | PSR_SVC32_MODE)
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msr cpsr, r0
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_PUTCHAR(Lconsole_pbase, r4, r3, 'a')
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/*
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* Set up a preliminary mapping in the MMU to allow us to run
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* at KERNEL_BASE with caches on.
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*/
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/* Build page table from scratch */
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ldr r0, Ltemp_l1_table
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mov r1, r0 /* Save the page table address. */
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/* Zero the entire table so all virtual addresses are invalid. */
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mov r2, #L1_TABLE_SIZE /* in bytes */
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mov r3, #0
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mov r4, r3
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mov r5, r3
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mov r6, r3
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mov r7, r3
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mov r8, r3
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mov r10, r3
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mov r11, r3
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1: stmia r1!, {r3-r8,r10-r11}
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stmia r1!, {r3-r8,r10-r11}
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stmia r1!, {r3-r8,r10-r11}
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stmia r1!, {r3-r8,r10-r11}
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subs r2, r2, #(4 * 4 * 8) /* bytes per loop */
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bne 1b
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_PUTCHAR(Lconsole_pbase, r4, r3, 'b')
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/* Now create our entries per the mmu_init_table. */
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l1table .req r0
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va .req r1
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pa .req r2
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n_sec .req r3
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attr .req r4
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itable .req r5
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l1sfrm .req r6
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ldr l1table, Ltemp_l1_table
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adr itable, mmu_init_table
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ldr l1sfrm, Ll1_s_frame
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b 3f
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2: str pa, [l1table, va]
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add va, va, #4
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add pa, pa, #(L1_S_SIZE)
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adds n_sec, n_sec, #-1
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bhi 2b
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3: ldmia itable!, {va,pa,n_sec,attr}
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/* Convert va to l1 offset: va = 4 * (va >> L1_S_SHIFT) */
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mov va, va, LSR #L1_S_SHIFT
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mov va, va, LSL #2
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/* Convert pa to l1 entry: pa = (pa & L1_S_FRAME) | attr */
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and pa, pa, l1sfrm
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orr pa, pa, attr
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cmp n_sec, #0
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bne 2b
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mov r5, r0 /* l1table */
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.unreq va
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.unreq pa
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.unreq n_sec
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.unreq attr
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.unreq itable
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.unreq l1table
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.unreq l1sfrm
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_PUTCHAR(Lconsole_pbase, r4, r3, 'c')
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/*
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* using FA526 -specific cache ops here...
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*/
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0 /* Invalidate Entire I cache */
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mcr p15, 0, r0, c7, c14, 0 /* Clean & Invalidate Entire D cache */
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ldr r2, Lctl_ID_dis /* Disable I+D caches */
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mrc p15, 0, r1, c1, c0, 0 /* " " " */
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and r1, r1, r2 /* " " " */
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mcr p15, 0, r1, c1, c0, 0 /* " " " */
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_PUTCHAR(Lconsole_pbase, r4, r3, 'd')
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mcr p15, 0, r0, c7, c5, 6 /* invalidate BTB all */
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mcr p15, 0, r0, c7, c10, 4 /* Drain the write buffers. */
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mcr p15, 0, r5, c2, c0, 0 /* Set Translation Table Base */
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mcr p15, 0, r0, c8, c7, 0 /* Invalidate TLBs */
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/* Set the Domain Access register */
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mov r0, #((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT)
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mcr p15, 0, r0, c3, c0, 0
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/*
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* set Extension Control Enable in ECR, so we can use BTB
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*/
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ldr r0, Lecr_set
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mcr p15, 0, r0, c1, c1, 0
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/*
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* Enable the MMU, etc.
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*/
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mrc p15, 0, r0, c1, c0, 0
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ldr r1, Lcontrol_wax
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and r0, r0, r1
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ldr r1, Lcontrol_clr
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mvn r1, r1
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and r0, r0, r1
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ldr r1, Lcontrol_set
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orr r0, r0, r1
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mcr p15, 0, r0, c1, c0, 0
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/*
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* Ensure that the coprocessor has finished turning on the MMU.
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*/
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mrc p15, 0, r0, c2, c0, 0 /* Read an arbitrary value. */
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mov r0, r0 /* Stall until read completes. */
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_PUTCHAR(Luart_vbase, r4, r3, 'e')
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/*
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* Zero .bss
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*/
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ldr r0, L_edata
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ldr r1, L_end
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mov r2, #0
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1:
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str r2, [r0], #0x04 /* *r0++ = r2 */
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cmp r0, r1
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bne 1b
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#if 0
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/*
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* Jump to start in locore.S, which in turn will call initarm and main.
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*/
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adr r0, Ltestjmp
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ldr pc, [r0]
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nop
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nop
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nop
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nop
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testjmp:
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#endif
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_PUTCHAR(Luart_vbase, r4, r3, 'f')
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adr r0, Lstart
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ldr pc, [r0]
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nop
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nop
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nop
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nop
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/* NOTREACHED */
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L_edata:
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.word _C_LABEL(_edata)
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L_end:
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.word _C_LABEL(_end)
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#if 0
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Ltestjmp:
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.word testjmp
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#endif
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Lstart:
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.word start
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Ll1_s_frame:
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.word L1_S_FRAME
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Ltemp_l1_table:
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/* Put the temporary L1 translation table at the end of SDRAM. */
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.word MEMSIZE * 0x100000 - L1_TABLE_SIZE
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/*
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* Coprocessor register initialization values
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*/
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#if !defined(CPU_ECR_ECE)
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# define CPU_ECR_ECE 1
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#endif
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/* bits to set in the Extension Control Register */
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Lecr_set:
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.word CPU_ECR_ECE
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#if !defined(CPU_CONTROL_BTB_ENABLE)
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# define CPU_CONTROL_BTB_ENABLE (1 << 11)
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#endif
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/* bits to set in the Control Register */
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/* bits 6..4 SB1 */
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Lcontrol_set:
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.word CPU_CONTROL_MMU_ENABLE | \
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CPU_CONTROL_AFLT_ENABLE | \
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CPU_CONTROL_DC_ENABLE | \
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CPU_CONTROL_WBUF_ENABLE | \
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CPU_CONTROL_32BP_ENABLE | \
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CPU_CONTROL_32BD_ENABLE | \
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CPU_CONTROL_LABT_ENABLE | \
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CPU_CONTROL_SYST_ENABLE | \
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CPU_CONTROL_IC_ENABLE | \
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CPU_CONTROL_DC_ENABLE | \
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CPU_CONTROL_BTB_ENABLE
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/* bits to clear in the Control Register */
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/* bits 31..14, 10, SBZ */
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Lcontrol_clr:
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.word ((~0) << 14) | \
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(1 << 10)
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/* bits to "write as existing" in the Control Register */
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Lcontrol_wax:
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.word CPU_CONTROL_BEND_ENABLE
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/* bits to disable the caches */
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Lctl_ID_dis:
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.word ~(CPU_CONTROL_IC_ENABLE|CPU_CONTROL_DC_ENABLE)
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/* console addressing */
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Lconsole_pbase:
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#if 0
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.word CONSADDR
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#else
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.word GEMINI_UART_BASE
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#endif
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Luart_vbase:
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.word GEMINI_UART_VBASE
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/* We'll modify va and pa at run time so we can use relocatable addresses. */
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#define MMU_INIT(va,pa,n_sec,attr) \
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.word va ; \
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.word pa ; \
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.word n_sec ; \
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.word attr ;
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mmu_init_table:
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/* Maintain current 1:1 addressability */
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MMU_INIT(KERNEL_BASE_phys, KERNEL_BASE_phys,
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(MEMSIZE * L1_S_SIZE + L1_S_SIZE - 1) / L1_S_SIZE,
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L1_S_PROTO | L1_S_AP(AP_KRW) | L1_S_B | L1_S_C)
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/* Map Kernel base VA:PA, write-back cacheable */
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MMU_INIT(KERNEL_BASE_virt, KERNEL_BASE_phys,
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(MEMSIZE * L1_S_SIZE + L1_S_SIZE - 1) / L1_S_SIZE,
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L1_S_PROTO | L1_S_AP(AP_KRW) | L1_S_B | L1_S_C)
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/* Map Gemini GLOBAL regs */
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MMU_INIT(GEMINI_GLOBAL_VBASE, GEMINI_GLOBAL_BASE,
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1,
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L1_S_PROTO | L1_S_AP(AP_KRW))
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/* Map Gemini UART */
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MMU_INIT(GEMINI_UART_VBASE, GEMINI_UART_BASE,
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1,
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L1_S_PROTO | L1_S_AP(AP_KRW))
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/* Map Gemini LPC Host Controlr Space */
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MMU_INIT(GEMINI_LPCHC_VBASE, GEMINI_LPCHC_BASE,
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1,
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L1_S_PROTO | L1_S_AP(AP_KRW))
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/* Map Gemini LPC IO Space */
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MMU_INIT(GEMINI_LPCIO_VBASE, GEMINI_LPCIO_BASE,
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1,
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L1_S_PROTO | L1_S_AP(AP_KRW))
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/* end of table */
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MMU_INIT(0, 0, 0, 0)
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