0a75e5a609
- New home of the RC7500 specific es driver. Moved with revision history
from mainbus.
- Really this driver should utilise the MI 91C90 driver and one day if
I can get hold of some hardware to test with I will update it.
266 lines
10 KiB
C
266 lines
10 KiB
C
/* $NetBSD: if_esreg.h,v 1.2 1997/10/14 21:45:24 mark Exp $ */
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/*
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* Copyright (c) 1996, Danny C Tsen.
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* Copyright (c) 1996, VLSI Technology Inc. All Rights Reserved.
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* Copyright (c) 1995 Michael L. Hitch
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Michael L. Hitch.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _IF_ESREG_H_
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#define _IF_ESREG_H_
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/*
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* This file is modified from Amiga's es driver for RC7500 board.
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* Each register of the SMC 91C92 is 16 bits wide and 4 bytes aligned.
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*/
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/*
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* SMC 91C9x register definitions
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*/
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union smcregs {
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struct {
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volatile u_int tcr; /* Transmit Control Register */
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volatile u_int ephsr; /* EPH Status Register */
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volatile u_int rcr; /* Receive Control Register */
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volatile u_int ecr; /* Counter Register */
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volatile u_int mir; /* Memory Information Register */
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volatile u_int mcr; /* Memory Configuration Register */
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volatile u_int resv;
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volatile u_int bsr; /* Bank Select Register */
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} b0;
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struct {
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volatile u_int cr; /* Configuration Register */
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volatile u_int bar; /* Base Address Register */
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volatile u_int iar[3]; /* Individual Address Registers */
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volatile u_int gpr; /* General Purpose Register */
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volatile u_int ctr; /* Control Register */
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volatile u_int bsr; /* Bank Select Register */
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} b1;
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struct {
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volatile u_int mmucr; /* MMU Command Register */
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volatile u_char pnr; /* Lo: Packet Number Register */
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volatile u_char arr; /* Hi: Allocation Result Register */
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volatile u_short pad0; /* padded to 4 bytes aligned */
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volatile u_int fifo; /* FIFO Ports Register */
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volatile u_int ptr; /* Pointer Register */
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volatile u_int data; /* Data Register */
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volatile u_int datax; /* Data Register (2nd mapping) */
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volatile u_char ist; /* Lo: Interrupt Status Register */
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volatile u_char msk; /* Hi: Interrupt Mask Register */
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volatile u_short pad1; /* padded to 4 bytes aligned */
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volatile u_int bsr; /* Bank Select Register */
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} b2;
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struct {
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volatile u_int mt[4]; /* Multicast Table */
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volatile u_int resv[3];
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volatile u_int bsr; /* Bank Select Register */
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} b3;
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/*
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* Bank 2 registers defined as u_int fields
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*/
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struct {
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volatile u_int mmucr; /* MMU Command Register */
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volatile u_int pnrarr;/* Packet Number/Allocation Result */
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volatile u_int fifo; /* FIFO Ports Register */
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volatile u_int ptr; /* Pointer Register */
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volatile u_int data; /* Data Register */
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volatile u_int datax; /* Data Register (2nd mapping) */
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volatile u_int istmsk;/* Interrupt Status/Mask Register */
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volatile u_int bsr; /* Bank Select Register */
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} w2;
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};
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/* Transmit Control Register */
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#define TCR_PAD_EN 0x0080 /* Pad short frames */
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#define TCR_TXENA 0x0001 /* Transmit enabled */
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#define TCR_MON_CSN 0x0400 /* Monitor carrier */
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#define TCR_FDUPLX 0x0800 /* Full duplex */
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/* EPH Status Register */
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#define EPHSR_16COL 0x0010 /* 16 collisions reached */
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#define EPHSR_MULCOL 0x0004 /* Multiple collsions */
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#define EPHSR_TX_SUC 0x0001 /* Last transmit sucessful */
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#define EPHSR_LOST_CAR 0x0400 /* Lost carrier */
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/* Receive Control Register */
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#define RCR_ALLMUL 0x0004 /* Accept all Multicast frames */
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#define RCR_PRMS 0x0002 /* Promiscuous mode */
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#define RCR_EPH_RST 0x8000 /* Software activated Reset */
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#define RCR_FILT_CAR 0x4000 /* Filter carrier */
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#define RCR_STRIP_CRC 0x0200 /* Strip CRC */
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#define RCR_RXEN 0x0100 /* Receiver enabled */
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/* Counter Register */
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#define ECR_CCMSK 0x00ff
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#define ECR_MCC 0x00f0 /* Multiple collision count */
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#define ECR_SCC 0x000f /* Single collision count */
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#define ECR_EDTX 0xf000 /* Excess deferred TX count */
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#define ECR_DTX 0x0f00 /* Deferred TX count */
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/* Configuration Register */
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#define CR_ALLONES 0x0030 /* 32Kx16 RAM */
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#define CR_RAM32K 0x0020 /* 32Kx16 RAM */
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#define CR_16BIT 0x0080 /* 16 bit bus */
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#define CR_NO_WAIT_ST 0x1000 /* No wait state */
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#define CR_SET_SQLCH 0x0200 /* Squelch level 240mv */
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/* Control Register */
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#define CTR_AUTO_RLSE 0x0800 /* Auto Release */
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/* MMU Command Register */
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#define MMUCR_NOOP 0x0000 /* No operation */
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#define MMUCR_ALLOC 0x0020 /* Allocate memory for TX */
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#define MMUCR_RESET 0x0040 /* Reset to intitial state */
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#define MMUCR_REM_RX 0x0060 /* Remove frame from top of RX FIFO */
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#define MMUCR_REMRLS_RX 0x0080 /* Remove & release from top of RX FIFO */
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#define MMUCR_RLSPKT 0x00a0 /* Release specific packet */
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#define MMUCR_ENQ_TX 0x00c0 /* Enqueue packet into TX FIFO */
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#define MMUCR_RESET_TX 0x00e0 /* Reset TX FIFOs */
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#define MMUCR_BUSY 0x0001 /* MMU busy */
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/* Allocation Result Register */
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#define ARR_FAILED 0x80 /* Allocation failed */
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#define ARR_APN 0x1f /* Allocated packet number */
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/* FIFO Ports Register */
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#define FIFO_TEMPTY 0x0080 /* TX queue empty */
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#define FIFO_TXPNR 0x001f /* TX done packet number */
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#define FIFO_REMPTY 0x8000 /* RX FIFO empty */
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#define FIFO_RXPNR 0x1f00 /* RX FIFO packet number */
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/* Pointer Register */
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#define PTR_RCV 0x8000 /* Use Receive area */
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#define PTR_AUTOINCR 0x4000 /* Auto increment pointer on access */
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#define PTR_READ 0x2000 /* Read access */
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/* Interrupt Status Register */
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#define IST_EPHINT 0x20 /* EPH Interrupt */
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#define IST_RX_OVRN 0x10 /* RX Overrun */
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#define IST_ALLOC 0x08 /* MMU Allocation completed */
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#define IST_TX_EMPTY 0x04 /* TX FIFO empty */
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#define IST_TX 0x02 /* TX complete */
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#define IST_RX 0x01 /* RX complete */
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/* Interrupt Acknowlege Register */
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#define ACK_RX_OVRN IST_RX_OVRN
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#define ACK_TX_EMPTY IST_TX_EMPTY
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#define ACK_TX IST_TX
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/* Interrupt Mask Register */
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#define MSK_EPHINT 0x20 /* EPH Interrupt */
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#define MSK_RX_OVRN 0x10 /* RX Overrun */
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#define MSK_ALLOC 0x08 /* MMU Allocation completed */
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#define MSK_TX_EMPTY 0x04 /* TX FIFO empty */
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#define MSK_TX 0x02 /* TX complete */
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#define MSK_RX 0x01 /* RX complete */
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/* Bank Select Register */
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#define BSR_BANK0 0x0000 /* Select bank 0 */
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#define BSR_BANK1 0x0001 /* Select bank 1 */
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#define BSR_BANK2 0x0002 /* Select bank 2 */
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#define BSR_BANK3 0x0003 /* Select bank 3 */
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#define BSR_BANKMSK 0x0003
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/* Packet Receive Frame Status Word */
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#define RFSW_ALGNERR 0x8000 /* Alignment Error */
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#define RFSW_BRDCST 0x4000 /* Broadcast frame */
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#define RFSW_BADCRC 0x2000 /* Bad CRC */
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#define RFSW_ODDFRM 0x1000 /* Odd number of bytes in frame */
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#define RFSW_TOOLNG 0x0800 /* Frame was too long */
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#define RFSW_TOOSHORT 0x0400 /* Frame was too short */
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#define RFSW_HASH 0x007e /* Multicast hash value */
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#define RFSW_MULTCAST 0x0001 /* Multicast frame */
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/* Control byte */
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#define CTLB_ODD 0x2000 /* Odd number of bytes in frame */
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#define CTLB_CRC 0x1000 /* Append CRC to transmitted frame */
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/*
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* The SMC 92C9x Register Definitions
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*/
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#define BANKSEL 0x1c /* The Bank Select Register (Read/Write) */
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#define BANK0 0x00
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#define BANK1 0x01
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#define BANK2 0x02
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#define BANK3 0x03
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/*
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* Register Bank #0 Definitions
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*/
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#define B0TCR 0x00 /* Transmit Control Register (Read/Write) */
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#define B0EPHSR 0x04 /* EPH Status Register (Read Only) */
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#define B0RCR 0x08 /* Receive Control Register (Read/Write) */
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#define B0ECR 0x0c /* Counter Register (Read Only) */
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#define B0MIR 0x10 /* Memory Information Register (Read Only) */
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#define B0MCR 0x14 /* Memory Configuration Register (Read/Write) */
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/*
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* Register Bank #1 Definitions
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*/
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#define B1CR 0x00 /* Configuration Register (Read/Write) */
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#define B1BAR 0x04 /* Base Address Register (Read/Write) */
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#define B1IAR1 0x08 /* Hi Individual Address Register #1 (R/W) */
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#define B1IAR2 0x09 /* Lo Individual Address Register #2 (R/W) */
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#define B1IAR3 0x0c /* Hi Individual Address Register #3 (R/W) */
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#define B1IAR4 0x0d /* Lo Individual Address Register #4 (R/W) */
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#define B1IAR5 0x10 /* Hi Individual Address Register #5 (R/W) */
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#define B1IAR6 0x11 /* Lo Individual Address Register #6 (R/W) */
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#define B1GPR 0x14 /* General Purpose Register (Read/Write) */
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#define B1CTR 0x18 /* Control Register (Read/Write) */
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/*
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* Register Bank #2 Definitions
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* NOTE: The Interrupt Mask Register occupies the upper byte of the
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* halfword read from or written to the IST or ACK Registers
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*/
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#define B2MMUCR 0x00 /* MMU Command Register (Read/Write) */
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#define B2PNR 0x04 /* Lo Packet Number Register (Read/Write) */
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#define B2ARR 0x05 /* Hi Allocation Result Register (Read Only) */
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#define B2FIFO 0x08 /* FIFO Ports Register (Read Only) */
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#define B2PTR 0x0c /* Pointer Register (Read/Write) */
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#define B2DATA 0x10 /* Data Register (Read/Write) */
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#define B2IST 0x18 /* Interrupt Status Register (Read Only) */
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#define B2ACK 0x18 /* Interrupt Acknowledge Register (Write) */
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#define B2MSK 0x19 /* Interrupt mask register, R/W */
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/*
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* Register Bank #3 Definitions
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*/
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#define B3MT0 0x00 /* Lo MultiCast Table #0 Register (R/W) */
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#define B3MT1 0x01 /* Hi MultiCast Table #1 Register (R/W) */
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#define B3MT2 0x04 /* Lo MultiCast Table #2 Register (R/W) */
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#define B3MT3 0x05 /* Hi MultiCast Table #3 Register (R/W) */
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#define B3MT4 0x08 /* Lo MultiCast Table #4 Register (R/W) */
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#define B3MT5 0x09 /* Hi MultiCast Table #5 Register (R/W) */
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#define B3MT6 0x0c /* Lo MultiCast Table #6 Register (R/W) */
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#define B3MT7 0x0d /* Hi MultiCast Table #7 Register (R/W) */
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#endif /* _IF_ESREG_H_ */
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