213 lines
5.9 KiB
C
213 lines
5.9 KiB
C
/* $NetBSD: pci_machdep.c,v 1.7 2010/03/18 13:58:38 kiyohara Exp $ */
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/*
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* Copyright (c) 1996 Christopher G. Demetriou. All rights reserved.
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* Copyright (c) 1994 Charles M. Hannum. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Charles M. Hannum.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Machine-specific functions for PCI autoconfiguration.
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*
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* On PCs, there are two methods of generating PCI configuration cycles.
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* We try to detect the appropriate mechanism for this machine and set
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* up a few function pointers to access the correct method directly.
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*
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* The configuration method can be hard-coded in the config file by
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* using `options PCI_CONF_MODE=N', where `N' is the configuration mode
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* as defined section 3.6.4.1, `Generating Configuration Cycles'.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: pci_machdep.c,v 1.7 2010/03/18 13:58:38 kiyohara Exp $");
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#include <sys/types.h>
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#include <sys/param.h>
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#include <sys/time.h>
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#include <sys/systm.h>
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#include <sys/errno.h>
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#include <sys/device.h>
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#include <sys/extent.h>
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#include <uvm/uvm_extern.h>
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcidevs.h>
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#include <dev/pci/pciconf.h>
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#include <powerpc/ibm4xx/ibm405gp.h>
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#include <powerpc/ibm4xx/dev/pcicreg.h>
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static struct powerpc_bus_space pci_iot = {
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_BUS_SPACE_LITTLE_ENDIAN | _BUS_SPACE_MEM_TYPE,
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0x00000000,
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IBM405GP_PCIC0_BASE, /* extent base */
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IBM405GP_PCIC0_BASE + 8, /* extent limit */
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};
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static bus_space_handle_t pci_ioh;
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void
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pci_machdep_init(void)
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{
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if (pci_ioh == 0 &&
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(bus_space_init(&pci_iot, "pcicfg", NULL, 0) ||
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bus_space_map(&pci_iot, IBM405GP_PCIC0_BASE, 8, 0, &pci_ioh)))
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panic("Cannot map PCI registers");
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}
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void
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pci_attach_hook(struct device *parent, struct device *self,
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struct pcibus_attach_args *pba)
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{
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#ifdef PCI_CONFIGURE_VERBOSE
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printf("pci_attach_hook\n");
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ibm4xx_show_pci_map();
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#endif
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ibm4xx_setup_pci();
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#ifdef PCI_CONFIGURE_VERBOSE
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ibm4xx_show_pci_map();
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#endif
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}
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pcitag_t
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pci_make_tag(pci_chipset_tag_t pc, int bus, int device, int function)
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{
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pcitag_t tag;
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if (bus >= 256 || device >= 32 || function >= 8)
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panic("pci_make_tag: bad request");
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/* XXX magic number */
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tag = 0x80000000 | (bus << 16) | (device << 11) | (function << 8);
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return tag;
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}
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void
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pci_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag, int *bp, int *dp, int *fp)
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{
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if (bp != NULL)
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*bp = (tag >> 16) & 0xff;
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if (dp != NULL)
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*dp = (tag >> 11) & 0x1f;
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if (fp != NULL)
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*fp = (tag >> 8) & 0x07;
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}
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pcireg_t
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pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg)
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{
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pcireg_t data;
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/* 405GT BIOS disables interrupts here. Should we? --Art */
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bus_space_write_4(&pci_iot, pci_ioh, PCIC_CFGADDR, tag | reg);
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data = bus_space_read_4(&pci_iot, pci_ioh, PCIC_CFGDATA);
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/* 405GP pass2 errata #6 */
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bus_space_write_4(&pci_iot, pci_ioh, PCIC_CFGADDR, 0);
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return data;
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}
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void
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pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t data)
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{
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bus_space_write_4(&pci_iot, pci_ioh, PCIC_CFGADDR, tag | reg);
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bus_space_write_4(&pci_iot, pci_ioh, PCIC_CFGDATA, data);
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/* 405GP pass2 errata #6 */
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bus_space_write_4(&pci_iot, pci_ioh, PCIC_CFGADDR, 0);
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}
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const char *
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pci_intr_string(pci_chipset_tag_t pc, pci_intr_handle_t ih)
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{
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static char irqstr[8]; /* 4 + 2 + NUL + sanity */
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/* Make sure it looks sane, intr_establish does the real check. */
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if (ih < 0 || ih > 99)
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panic("pci_intr_string: handle %d won't fit two digits", ih);
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sprintf(irqstr, "irq %d", ih);
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return (irqstr);
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}
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const struct evcnt *
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pci_intr_evcnt(pci_chipset_tag_t pc, pci_intr_handle_t ih)
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{
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/* XXX for now, no evcnt parent reported */
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return NULL;
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}
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int
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pci_intr_setattr(pci_chipset_tag_t pc, pci_intr_handle_t *ih,
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int attr, uint64_t data)
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{
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switch (attr) {
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case PCI_INTR_MPSAFE:
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return 0;
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default:
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return ENODEV;
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}
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}
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void *
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pci_intr_establish(pci_chipset_tag_t pc, pci_intr_handle_t ih, int level,
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int (*func)(void *), void *arg)
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{
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return intr_establish(ih, IST_LEVEL, level, func, arg);
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}
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void
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pci_intr_disestablish(pci_chipset_tag_t pc, void *cookie)
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{
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intr_disestablish(cookie);
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}
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/* Avoid overconfiguration */
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int
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pci_conf_hook(pci_chipset_tag_t pc, int bus, int dev, int func, pcireg_t id)
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{
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if ((PCI_VENDOR(id) == PCI_VENDOR_IBM && PCI_PRODUCT(id) == PCI_PRODUCT_IBM_405GP) ||
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(PCI_VENDOR(id) == PCI_VENDOR_INTEL && PCI_PRODUCT(id) == PCI_PRODUCT_INTEL_80960_RP)) {
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/* Don't configure the bridge and PCI probe. */
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return 0;
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}
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return PCI_CONF_DEFAULT;
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}
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