168 lines
6.6 KiB
C
168 lines
6.6 KiB
C
/* $NetBSD: gpiicreg.h,v 1.2 2005/12/11 12:18:42 christos Exp $ */
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/* Original Tag: iicreg.h,v 1.3 2003/09/23 14:56:08 shige Exp */
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/*
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* Copyright 2001 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Simon Burge and Eduardo Horvath for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _IBM4XX_GPIICREG_H_
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#define _IBM4XX_GPIICREG_H_
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/* IIC FIFO buffer size */
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#define IIC_FIFO_BUFSIZE (4)
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/*
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* definitions for IIC Addressing Mode
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*/
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#define IIC_LADR_SHFT 1 /* LowAddr (7-bit addressing) shift */
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#define IIC_HADR_SHFT 1 /* HighAddr (10-bit addressing) shift */
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/*
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* definitions for IIC Registers
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*/
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#define IIC_MDBUF 0x00 /* Master Data Buffer */
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#define IIC_SDBUF 0x02 /* Slave Data Buffer */
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#define IIC_LMADR 0x04 /* Low Master Address */
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#define IIC_HMADR 0x05 /* High Master Address */
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#define IIC_CNTL 0x06 /* Control */
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#define IIC_MDCNTL 0x07 /* Mode Control */
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#define IIC_STS 0x08 /* Status */
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#define IIC_EXTSTS 0x09 /* Extended Status */
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#define IIC_LSADR 0x0a /* Low Slave Address */
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#define IIC_HSADR 0x0b /* High Slave Address */
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#define IIC_CLKDIV 0x0c /* Clock Divide */
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#define IIC_INTRMSK 0x0d /* Interrupt Mask */
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#define IIC_XFRCNT 0x0e /* Transfer Count */
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#define IIC_XTCNTLSS 0x0f /* Extended Control and Slave Status */
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#define IIC_DIRECTCNTL 0x10 /* Direct Control */
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#define IIC_NREG 0x20
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/*
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* Bit definitions for IIC_CNTL
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*/
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#define IIC_CNTL_PT (1u << 0) /* Pending Transfer */
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#define IIC_CNTL_RW (1u << 1) /* Read/Write */
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#define IIC_CNTL_CHT (1u << 2) /* Chain Transfer */
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#define IIC_CNTL_RPST (1u << 3) /* Repeated Start */
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#define IIC_CNTL_TCT (3u << 4) /* Transfer Count */
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#define IIC_CNTL_AMD (1u << 6) /* Addressing Mode */
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#define IIC_CNTL_HMT (1u << 7) /* Halt Master Transfer */
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#define IIC_CNTL_TCT_SHFT 4
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/*
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* Bit definitions for IIC_MDCNTL
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*/
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#define IIC_MDCNTL_HSCL (1u << 0) /* Hold IIC Serial Clock Low */
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#define IIC_MDCNTL_EUBS (1u << 1) /* Exit Unknown IIC Bus State */
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#define IIC_MDCNTL_EINT (1u << 2) /* Enable Interrupt */
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#define IIC_MDCNTL_ESM (1u << 3) /* Enable Slave Mode */
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#define IIC_MDCNTL_FSM (1u << 4) /* Fast/Standard Mode */
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#define IIC_MDCNTL_FMDB (1u << 6) /* Flush Master Data Buffer */
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#define IIC_MDCNTL_FSDB (1u << 7) /* Flush Slave Data Buffer */
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/*
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* Bit definitions for IIC_STS
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*/
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#define IIC_STS_PT (1u << 0) /* RO:Pending Transfer */
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#define IIC_STS_IRQA (1u << 1) /* IRQ Active */
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#define IIC_STS_ERR (1u << 2) /* RO:Error */
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#define IIC_STS_SCMP (1u << 3) /* Stop Complete */
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#define IIC_STS_MDBF (1u << 4) /* RO:MasterDataBuffer Full */
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#define IIC_STS_MDBS (1u << 5) /* RO:MasterDataBuffer Status */
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#define IIC_STS_SLPR (1u << 6) /* Sleep Request */
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#define IIC_STS_SSS (1u << 7) /* Slave Status Set */
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/*
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* Bit definitions for IIC_EXTSTS
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*/
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#define IIC_EXTSTS_XFRA (1u << 0) /* Transfer Aborted */
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#define IIC_EXTSTS_ICT (1u << 1) /* Incomplete Transfer */
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#define IIC_EXTSTS_LA (1u << 2) /* Lost Arbitration */
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#define IIC_EXTSTS_IRQD (1u << 3) /* IRQ On-Deck */
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#define IIC_EXTSTS_BCS (7u << 4) /* RO:Bus Control State */
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#define IIC_EXTSTS_IRQP (1u << 7) /* IRQ Pending */
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#define IIC_EXTSTS_BCS_FREE (4u << 4) /* BCS: Free Bus */
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/*
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* Bit definitions for IIC_XFRCNT
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*/
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#define IIC_INTRMSK_EIMTC (1u << 0) /* Enable IRQ on Reqested MT */
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#define IIC_INTRMSK_EITA (1u << 1) /* Enable IRQ on Trans Abort */
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#define IIC_INTRMSK_EIIC (1u << 2) /* Enable IRQ on Incomp*/
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#define IIC_INTRMSK_EIHE (1u << 3) /* */
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#define IIC_INTRMSK_EIWS (1u << 4) /* */
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#define IIC_INTRMSK_EIWC (1u << 5) /* */
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#define IIC_INTRMSK_EIRS (1u << 6) /* */
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#define IIC_INTRMSK_EIRC (1u << 7) /* */
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/*
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* Bit definitions for IIC_XFRCNT
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*/
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#define IIC_XFRCNT_STC (7u << 4) /* Slave Transfer Count */
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#define IIC_XFRCNT_MTC (7u << 0) /* Master Transfer Count */
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#define IIC_XFRCNT_STC_SHFT 4
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/*
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* Bit definitions for IIC_XTCNTLSS
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*/
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#define IIC_XTCNTLSS_SRST (1u << 0) /* Soft reset */
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#define IIC_XTCNTLSS_EPI (1u << 1) /* Enable pulsed IRQ */
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#define IIC_XTCNTLSS_SDBF (1u << 2) /* Slave data buffer full */
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#define IIC_XTCNTLSS_SDBD (1u << 3) /* Slave data buffer has data */
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#define IIC_XTCNTLSS_SWS (1u << 4) /* Slave write needs service */
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#define IIC_XTCNTLSS_SWC (1u << 5) /* Slave write complete */
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#define IIC_XTCNTLSS_SRS (1u << 6) /* Slave read needs service */
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#define IIC_XTCNTLSS_SRC (1u << 7) /* Slave read complete */
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/*
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* Bit definitions for IIC_DIRECTCNTL
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*/
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#define IIC_DIRECTCNTL_MSC (1u << 0) /* Monitor IIC Clock Line (ro)*/
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#define IIC_DIRECTCNTL_MSDA (1u << 1) /* Monitor IIC Data Line (ro) */
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#define IIC_DIRECTCNTL_SCC (1u << 2) /* IIC Clock Control */
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#define IIC_DIRECTCNTL_SDAC (1u << 3) /* IIC Data Control */
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/*
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* Value definitions for IIC_CLKDIV
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*/
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#define IIC_CLKDIV_20MHZ (0x01) /* OPB f = 20 MHz */
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#define IIC_CLKDIV_30MHZ (0x02) /* OPB 20 < f <= 30 MHz */
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#define IIC_CLKDIV_40MHZ (0x03) /* OPB 30 < f <= 40 MHz */
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#define IIC_CLKDIV_50MHZ (0x04) /* OPB 40 < f <= 50 MHz */
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#define IIC_CLKDIV_60MHZ (0x05) /* OPB 50 < f <= 60 MHz */
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#define IIC_CLKDIV_70MHZ (0x06) /* OPB 60 < f <= 70 MHz */
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#endif /* _IBM4XX_GPIICREG_H_ */
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