94 lines
3.3 KiB
C
94 lines
3.3 KiB
C
/* $NetBSD: clockreg.h,v 1.11 2011/02/08 20:20:13 rmind Exp $ */
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/*
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* Copyright (c) 1988 University of Utah.
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* Copyright (c) 1982, 1990, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* the Systems Programming Group of the University of Utah Computer
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* Science Department.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: Utah $Hdr: clockreg.h 1.14 91/01/18$
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*
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* @(#)clockreg.h 8.2 (Berkeley) 1/12/94
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*/
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/*
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* MC6840 PTM registers
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*/
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struct clkreg {
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u_char clk_dummy1;
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u_char clk_cr3;
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#define clk_cr1 clk_cr3
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u_char clk_dummy2;
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u_char clk_cr2;
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#define clk_sr clk_cr2
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u_char clk_dummy3;
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u_char clk_msb1;
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u_char clk_dummy4;
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u_char clk_lsb1;
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u_char clk_dummy5;
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u_char clk_msb2;
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u_char clk_dummy6;
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u_char clk_lsb2;
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u_char clk_dummy7;
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u_char clk_msb3;
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u_char clk_dummy8;
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u_char clk_lsb3;
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};
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/* base/offsets for register access (for locore.s) */
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#define CLKBASE IIOPOFF(0x5F8000)
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#define CLKCR1 0x1
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#define CLKCR2 0x3
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#define CLKCR3 CLKCR1
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#define CLKSR CLKCR2
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#define CLKMSB1 0x5
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#define CLKMSB2 0x9
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#define CLKMSB3 0xD
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/* output of counter 3 clocks counter 2 */
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#define CLK_OENAB 0x80 /* output enable */
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#define CLK_IENAB 0x40 /* interrupt enable */
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#define CLK_8BIT 0x04 /* 8 bit mode */
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#define CLK_RESET 0x01 /* chip reset (CR1 only) */
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#define CLK_CR1 0x01 /* select CR1 (CR2 only) */
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#define CLK_CR3 0x00 /* select CR3 (CR2 only) */
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#define CLK_INT1 0x01 /* interrupt flag for timer 1 (SR only) */
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#define CLK_INT2 0x02 /* interrupt flag for timer 2 (SR only) */
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#define CLK_INT3 0x04 /* interrupt flag for timer 3 (SR only) */
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#define CLK_INTR 0x80 /* composite interrupt flag (SR only) */
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#define CLK_RESOLUTION 4 /* 4 usec resolution (250 kHz) */
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#define CLK_INTERVAL 2500 /* 10msec interval at 250 kHz */
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#ifdef NOTDEF
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#define CLK_INTERVAL 5000 /* 20msec interval at 250 kHz */
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#endif
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