190 lines
5.7 KiB
C
190 lines
5.7 KiB
C
/* $NetBSD: dbrivar.h,v 1.10 2008/05/16 15:38:20 macallan Exp $ */
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/*
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* Copyright (C) 1997 Rudolf Koenig (rfkoenig@immd4.informatik.uni-erlangen.de)
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* Copyright (c) 1998, 1999 Brent Baccala (baccala@freesoft.org)
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* Copyright (c) 2001, 2002 Jared D. McNeill <jmcneill@netbsd.org>
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* Copyright (c) 2005 Michael Lorenz <macallan@netbsd.org>
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* All rights reserved.
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*
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* This driver is losely based on a Linux driver written by Rudolf Koenig and
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* Brent Baccala who kindly gave their permission to use their code in a
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* BSD-licensed driver.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#ifndef DBRI_VAR_H
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#define DBRI_VAR_H
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#define DBRI_NUM_COMMANDS 64
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#define DBRI_NUM_DESCRIPTORS 32
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#define DBRI_INT_BLOCKS 64
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#define DBRI_PIPE_MAX 32
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enum direction {
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in,
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out
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};
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/* DBRI DMA transmit descriptor */
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struct dbri_xmit {
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volatile uint32_t flags;
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#define TX_EOF 0x80000000 /* End of frame marker */
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#define TX_BCNT(x) ((x&0x3fff)<<16)
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#define TX_BINT 0x00008000 /* interrupt when EOF */
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#define TX_MINT 0x00004000 /* marker interrupt */
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#define TX_IDLE 0x00002000 /* send idles after data */
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#define TX_FCNT(x) (x&0x1fff)
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volatile uint32_t ba; /* tx/rx buffer address */
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volatile uint32_t nda; /* next descriptor address */
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volatile uint32_t status;
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#define TS_OK 0x0001 /* transmission completed */
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#define TS_ABORT 0x0004 /* transmission aborted */
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#define TS_UNDERRUN 0x0008 /* DMA underrun */
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};
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struct dbri_recv {
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volatile uint32_t status;
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#define RX_EOF 0x80000000
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#define RX_COMPLETED 0x40000000
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#define RX_BCNT(x) ((x & 0x3fff) << 16)
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#define RX_CRCERROR 0x00000080
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#define RX_BBC 0x00000040 /* bad byte count */
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#define RX_ABORT 0x00000020
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#define RX_OVERRUN 0x00000008
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volatile uint32_t ba;
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volatile uint32_t nda;
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volatile uint32_t flags;
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#define RX_BSIZE(x) (x & 0x3fff)
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#define RX_FINAL 0x00008000
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#define RX_MARKER 0x00004000
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};
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struct dbri_pipe {
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uint32_t sdp; /* SDP command word */
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enum direction direction;
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int next; /* next pipe in linked list */
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int prev; /* previous pipe in linked list */
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int cycle; /* offset of timeslot (bits) */
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int length; /* length of timeslot (bits) */
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int desc; /* index of active descriptor */
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volatile uint32_t *prec; /* pointer to received fixed data */
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};
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struct dbri_desc {
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int busy;
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void * buf; /* cpu view of buffer */
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void * buf_dvma; /* device view */
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bus_addr_t dmabase;
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bus_dma_segment_t dmaseg;
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bus_dmamap_t dmamap;
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size_t len;
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void (*callback)(void *);
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void *callback_args;
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void *softint;
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};
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struct dbri_dma {
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volatile uint32_t command[DBRI_NUM_COMMANDS];
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volatile int32_t intr[DBRI_INT_BLOCKS];
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struct dbri_xmit xmit[DBRI_NUM_DESCRIPTORS];
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struct dbri_recv recv[DBRI_NUM_DESCRIPTORS];
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};
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struct dbri_softc {
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device_t sc_dev; /* base device */
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struct sbusdev sc_sd; /* sbus device */
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bus_space_handle_t sc_ioh;
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bus_space_tag_t sc_iot;
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/* DMA buffer for sending commands to the chip */
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bus_dma_tag_t sc_dmat;
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bus_dmamap_t sc_dmamap;
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bus_dma_segment_t sc_dmaseg;
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int sc_have_powerctl;
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int sc_powerstate; /* DBRI's powered up or not */
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int sc_pmgrstate; /* PWR_RESUME etc. */
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int sc_burst; /* DVMA burst size in effect */
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bus_addr_t sc_dmabase; /* VA of buffer we provide */
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void * sc_membase;
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int sc_bufsiz; /* size of the buffer */
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int sc_locked;
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int sc_irqp;
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int sc_waitseen;
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int sc_refcount;
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int sc_playing;
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int sc_recording;
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int sc_liu_state;
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void (*sc_liu)(void *);
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void *sc_liu_args;
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struct dbri_pipe sc_pipe[DBRI_PIPE_MAX];
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struct dbri_desc sc_desc[DBRI_NUM_DESCRIPTORS];
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struct cs4215_state sc_mm;
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int sc_latt, sc_ratt; /* output attenuation */
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int sc_linp, sc_rinp; /* input volume */
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int sc_monitor; /* monitor volume */
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int sc_input; /* 0 - line, 1 - mic */
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int sc_ctl_mode;
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uint32_t sc_version;
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int sc_chi_pipe_in;
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int sc_chi_pipe_out;
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int sc_chi_bpf;
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int sc_desc_used;
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struct audio_params sc_params;
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struct dbri_dma *sc_dma;
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};
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#define dbri_dma_off(member, elem) \
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((uint32_t)(unsigned long) \
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(&(((struct dbri_dma *)0)->member[elem])))
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#if 1
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#define DBRI_CMD(cmd, intr, value) ((cmd << 28) | (intr << 27) | value)
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#else
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#define DBRI_CMD(cmd, intr, value) ((cmd << 28) | (1 << 27) | value)
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#endif
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#define DBRI_INTR_GETCHAN(v) (((v) >> 24) & 0x3f)
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#define DBRI_INTR_GETCODE(v) (((v) >> 20) & 0xf)
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#define DBRI_INTR_GETCMD(v) (((v) >> 16) & 0xf)
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#define DBRI_INTR_GETVAL(v) ((v) & 0xffff)
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#define DBRI_INTR_GETRVAL(v) ((v) & 0xfffff)
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#define DBRI_SDP_MODE(v) ((v) & (7 << 13))
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#define DBRI_PIPE(v) ((v) << 0)
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#endif /* DBRI_VAR_H */
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