280 lines
9.1 KiB
C
280 lines
9.1 KiB
C
/* $NetBSD: pcivar.h,v 1.83 2008/07/22 04:52:19 bjs Exp $ */
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/*
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* Copyright (c) 1996, 1997 Christopher G. Demetriou. All rights reserved.
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* Copyright (c) 1994 Charles M. Hannum. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Charles M. Hannum.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _DEV_PCI_PCIVAR_H_
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#define _DEV_PCI_PCIVAR_H_
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/*
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* Definitions for PCI autoconfiguration.
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*
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* This file describes types and functions which are used for PCI
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* configuration. Some of this information is machine-specific, and is
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* provided by pci_machdep.h.
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*/
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#include <sys/device.h>
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#include <sys/pmf.h>
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#include <sys/bus.h>
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#include <dev/pci/pcireg.h>
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/*
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* Structures and definitions needed by the machine-dependent header.
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*/
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typedef u_int32_t pcireg_t; /* configuration space register XXX */
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struct pcibus_attach_args;
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struct pci_softc;
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#ifdef _KERNEL
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/*
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* Machine-dependent definitions.
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*/
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#include <machine/pci_machdep.h>
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/*
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* PCI bus attach arguments.
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*/
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struct pcibus_attach_args {
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char *_pba_busname; /* XXX placeholder */
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bus_space_tag_t pba_iot; /* pci i/o space tag */
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bus_space_tag_t pba_memt; /* pci mem space tag */
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bus_dma_tag_t pba_dmat; /* DMA tag */
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bus_dma_tag_t pba_dmat64; /* DMA tag */
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pci_chipset_tag_t pba_pc;
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int pba_flags; /* flags; see below */
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int pba_bus; /* PCI bus number */
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/*
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* Pointer to the pcitag of our parent bridge. If there is no
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* parent bridge, then we assume we are a root bus.
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*/
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pcitag_t *pba_bridgetag;
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/*
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* Interrupt swizzling information. These fields
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* are only used by secondary busses.
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*/
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u_int pba_intrswiz; /* how to swizzle pins */
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pcitag_t pba_intrtag; /* intr. appears to come from here */
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};
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/*
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* PCI device attach arguments.
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*/
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struct pci_attach_args {
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bus_space_tag_t pa_iot; /* pci i/o space tag */
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bus_space_tag_t pa_memt; /* pci mem space tag */
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bus_dma_tag_t pa_dmat; /* DMA tag */
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bus_dma_tag_t pa_dmat64; /* DMA tag */
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pci_chipset_tag_t pa_pc;
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int pa_flags; /* flags; see below */
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u_int pa_bus;
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u_int pa_device;
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u_int pa_function;
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pcitag_t pa_tag;
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pcireg_t pa_id, pa_class;
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/*
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* Interrupt information.
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*
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* "Intrline" is used on systems whose firmware puts
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* the right routing data into the line register in
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* configuration space. The rest are used on systems
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* that do not.
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*/
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u_int pa_intrswiz; /* how to swizzle pins if ppb */
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pcitag_t pa_intrtag; /* intr. appears to come from here */
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pci_intr_pin_t pa_intrpin; /* intr. appears on this pin */
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pci_intr_line_t pa_intrline; /* intr. routing information */
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pci_intr_pin_t pa_rawintrpin; /* unswizzled pin */
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};
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/*
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* Flags given in the bus and device attachment args.
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*/
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#define PCI_FLAGS_IO_ENABLED 0x01 /* I/O space is enabled */
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#define PCI_FLAGS_MEM_ENABLED 0x02 /* memory space is enabled */
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#define PCI_FLAGS_MRL_OKAY 0x04 /* Memory Read Line okay */
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#define PCI_FLAGS_MRM_OKAY 0x08 /* Memory Read Multiple okay */
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#define PCI_FLAGS_MWI_OKAY 0x10 /* Memory Write and Invalidate
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okay */
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/*
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* PCI device 'quirks'.
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*
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* In general strange behaviour which can be handled by a driver (e.g.
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* a bridge's inability to pass a type of access correctly) should be.
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* The quirks table should only contain information which impacts
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* the operation of the MI PCI code and which can't be pushed lower
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* (e.g. because it's unacceptable to require a driver to be present
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* for the information to be known).
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*/
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struct pci_quirkdata {
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pci_vendor_id_t vendor; /* Vendor ID */
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pci_product_id_t product; /* Product ID */
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int quirks; /* quirks; see below */
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};
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#define PCI_QUIRK_MULTIFUNCTION 1
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#define PCI_QUIRK_MONOFUNCTION 2
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#define PCI_QUIRK_SKIP_FUNC(n) (4 << n)
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#define PCI_QUIRK_SKIP_FUNC0 PCI_QUIRK_SKIP_FUNC(0)
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#define PCI_QUIRK_SKIP_FUNC1 PCI_QUIRK_SKIP_FUNC(1)
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#define PCI_QUIRK_SKIP_FUNC2 PCI_QUIRK_SKIP_FUNC(2)
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#define PCI_QUIRK_SKIP_FUNC3 PCI_QUIRK_SKIP_FUNC(3)
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#define PCI_QUIRK_SKIP_FUNC4 PCI_QUIRK_SKIP_FUNC(4)
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#define PCI_QUIRK_SKIP_FUNC5 PCI_QUIRK_SKIP_FUNC(5)
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#define PCI_QUIRK_SKIP_FUNC6 PCI_QUIRK_SKIP_FUNC(6)
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#define PCI_QUIRK_SKIP_FUNC7 PCI_QUIRK_SKIP_FUNC(7)
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struct pci_conf_state {
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pcireg_t reg[16];
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};
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struct pci_child {
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device_t c_dev;
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bool c_psok;
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pcireg_t c_powerstate;
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struct pci_conf_state c_conf;
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};
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struct pci_softc {
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device_t sc_dev;
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bus_space_tag_t sc_iot, sc_memt;
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bus_dma_tag_t sc_dmat;
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bus_dma_tag_t sc_dmat64;
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pci_chipset_tag_t sc_pc;
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int sc_bus, sc_maxndevs;
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pcitag_t *sc_bridgetag;
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u_int sc_intrswiz;
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pcitag_t sc_intrtag;
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int sc_flags;
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/* accounting of child devices */
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struct pci_child sc_devices[32*8];
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#define PCI_SC_DEVICESC(d, f) sc_devices[(d) * 8 + (f)]
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};
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extern struct cfdriver pci_cd;
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int pcibusprint(void *, const char *);
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/*
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* Configuration space access and utility functions. (Note that most,
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* e.g. make_tag, conf_read, conf_write are declared by pci_machdep.h.)
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*/
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int pci_mapreg_probe(pci_chipset_tag_t, pcitag_t, int, pcireg_t *);
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pcireg_t pci_mapreg_type(pci_chipset_tag_t, pcitag_t, int);
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int pci_mapreg_info(pci_chipset_tag_t, pcitag_t, int, pcireg_t,
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bus_addr_t *, bus_size_t *, int *);
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int pci_mapreg_map(struct pci_attach_args *, int, pcireg_t, int,
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bus_space_tag_t *, bus_space_handle_t *, bus_addr_t *,
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bus_size_t *);
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int pci_mapreg_submap(struct pci_attach_args *, int, pcireg_t, int,
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bus_size_t, bus_size_t, bus_space_tag_t *, bus_space_handle_t *,
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bus_addr_t *, bus_size_t *);
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int pci_find_rom(struct pci_attach_args *, bus_space_tag_t, bus_space_handle_t,
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int, bus_space_handle_t *, bus_size_t *);
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int pci_get_capability(pci_chipset_tag_t, pcitag_t, int, int *, pcireg_t *);
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/*
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* Helper functions for autoconfiguration.
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*/
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int pci_probe_device(struct pci_softc *, pcitag_t tag,
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int (*)(struct pci_attach_args *), struct pci_attach_args *);
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void pci_devinfo(pcireg_t, pcireg_t, int, char *, size_t);
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void pci_conf_print(pci_chipset_tag_t, pcitag_t,
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void (*)(pci_chipset_tag_t, pcitag_t, const pcireg_t *));
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const struct pci_quirkdata *
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pci_lookup_quirkdata(pci_vendor_id_t, pci_product_id_t);
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/*
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* Helper functions for user access to the PCI bus.
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*/
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struct proc;
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int pci_devioctl(pci_chipset_tag_t, pcitag_t, u_long, void *,
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int flag, struct lwp *);
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/*
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* Power Management (PCI 2.2)
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*/
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#define PCI_PWR_D0 0
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#define PCI_PWR_D1 1
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#define PCI_PWR_D2 2
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#define PCI_PWR_D3 3
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int pci_powerstate(pci_chipset_tag_t, pcitag_t, const int *, int *);
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/*
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* Vital Product Data (PCI 2.2)
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*/
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int pci_vpd_read(pci_chipset_tag_t, pcitag_t, int, int, pcireg_t *);
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int pci_vpd_write(pci_chipset_tag_t, pcitag_t, int, int, pcireg_t *);
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/*
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* Misc.
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*/
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const char *pci_findvendor(pcireg_t);
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const char *pci_findproduct(pcireg_t);
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int pci_find_device(struct pci_attach_args *pa,
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int (*match)(struct pci_attach_args *));
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int pci_dma64_available(struct pci_attach_args *);
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void pci_conf_capture(pci_chipset_tag_t, pcitag_t, struct pci_conf_state *);
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void pci_conf_restore(pci_chipset_tag_t, pcitag_t, struct pci_conf_state *);
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int pci_get_powerstate(pci_chipset_tag_t, pcitag_t, pcireg_t *);
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int pci_set_powerstate(pci_chipset_tag_t, pcitag_t, pcireg_t);
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int pci_activate(pci_chipset_tag_t, pcitag_t, device_t,
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int (*)(pci_chipset_tag_t, pcitag_t, device_t, pcireg_t));
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int pci_activate_null(pci_chipset_tag_t, pcitag_t, device_t, pcireg_t);
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void pci_disable_retry(pci_chipset_tag_t, pcitag_t);
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/*
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* Device abstraction for inheritance by elanpci(4), for example.
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*/
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int pcimatch(device_t, cfdata_t, void *);
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void pciattach(device_t, device_t, void *);
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int pcidetach(device_t, int);
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void pcidevdetached(device_t, device_t);
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int pcirescan(device_t, const char *, const int *);
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/*
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* Interrupts.
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*/
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#define PCI_INTR_MPSAFE 1
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int pci_intr_setattr(pci_chipset_tag_t, pci_intr_handle_t *, int, uint64_t);
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#endif /* _KERNEL */
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#endif /* _DEV_PCI_PCIVAR_H_ */
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