bc44c54090
properly. Modified slightly by me to add the pegasosreg.h file. With this change, the pegasos correctly scans both primary and secondary PCI busses.
265 lines
8.1 KiB
C
265 lines
8.1 KiB
C
/* $NetBSD: pegasospci.c,v 1.3 2007/11/04 17:07:10 garbled Exp $ */
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/*-
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* Copyright (c) 2007 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Tim Rightnour
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: pegasospci.c,v 1.3 2007/11/04 17:07:10 garbled Exp $");
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#include <sys/param.h>
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#include <sys/device.h>
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#include <sys/malloc.h>
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#include <sys/systm.h>
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#include <dev/pci/pcivar.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_pci.h>
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#include <machine/autoconf.h>
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#include <machine/pio.h>
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#include <machine/isa_machdep.h>
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#include <machine/pegasosreg.h>
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struct pegasospci_softc {
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struct device sc_dev;
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struct genppc_pci_chipset sc_pc;
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struct powerpc_bus_space sc_iot;
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struct powerpc_bus_space sc_memt;
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};
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static void pegasospci_attach(struct device *, struct device *, void *);
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static int pegasospci_match(struct device *, struct cfdata *, void *);
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static pcireg_t pegasospci_indirect_conf_read(void *, pcitag_t, int);
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static void pegasospci_indirect_conf_write(void *, pcitag_t, int, pcireg_t);
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CFATTACH_DECL(pegasospci, sizeof(struct pegasospci_softc),
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pegasospci_match, pegasospci_attach, NULL, NULL);
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extern struct genppc_pci_chipset *genppc_pct;
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static u_int32_t *pciagp_magic;
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static void
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pegasospci_get_chipset_tag(pci_chipset_tag_t pc)
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{
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pc->pc_conf_v = (void *)pc;
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pc->pc_attach_hook = genppc_pci_indirect_attach_hook;
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pc->pc_bus_maxdevs = genppc_pci_bus_maxdevs;
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pc->pc_make_tag = genppc_pci_indirect_make_tag;
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pc->pc_conf_read = genppc_pci_indirect_conf_read;
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pc->pc_conf_write = genppc_pci_indirect_conf_write;
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pc->pc_intr_v = (void *)pc;
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pc->pc_intr_map = genofw_pci_intr_map;
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pc->pc_intr_string = genppc_pci_intr_string;
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pc->pc_intr_evcnt = genppc_pci_intr_evcnt;
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pc->pc_intr_establish = genppc_pci_intr_establish;
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pc->pc_intr_disestablish = genppc_pci_intr_disestablish;
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pc->pc_conf_interrupt = genppc_pci_conf_interrupt;
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pc->pc_decompose_tag = genppc_pci_indirect_decompose_tag;
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pc->pc_conf_hook = genofw_pci_conf_hook;
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pc->pc_addr = 0;
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pc->pc_data = 0;
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pc->pc_bus = 0;
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pc->pc_node = 0;
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pc->pc_ihandle = 0;
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pc->pc_memt = 0;
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pc->pc_iot = 0;
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}
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static int
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pegasospci_match(struct device *parent, struct cfdata *cf, void *aux)
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{
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struct confargs *ca = aux;
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char name[32];
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int node;
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if (strcmp(ca->ca_name, "pci") != 0)
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return 0;
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memset(name, 0, sizeof(name));
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OF_getprop(ca->ca_node, "device_type", name, sizeof(name));
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if (strcmp(name, "pci") != 0)
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return 0;
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node = OF_finddevice("/");
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if (node < 0)
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return 0;
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memset(name, 0, sizeof(name));
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OF_getprop(node, "name", name, sizeof(name));
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if (strcmp(name, "bplan,Pegasos2") != 0)
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return 0;
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return 10;
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}
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static void
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pegasospci_attach(struct device *parent, struct device *self, void *aux)
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{
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struct pegasospci_softc *sc = (void *)self;
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pci_chipset_tag_t pc = &sc->sc_pc;
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struct confargs *ca = aux;
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struct pcibus_attach_args pba;
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struct genppc_pci_chipset_businfo *pbi;
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int isprim = 0, node = ca->ca_node;
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uint32_t reg[2], busrange[2];
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aprint_normal("\n");
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if (OF_getprop(node, "reg", reg, sizeof(reg)) < 8)
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return;
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/* PCI bus number */
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if (OF_getprop(node, "bus-range", busrange, sizeof(busrange)) != 8)
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return;
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/* bus space map the io ranges */
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sc->sc_iot.pbs_flags = _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_IO_TYPE;
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sc->sc_iot.pbs_base = 0x00000000;
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if (ofwoea_map_space(RANGE_TYPE_PCI, RANGE_IO, node, &sc->sc_iot,
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"pegasospci io-space") != 0)
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panic("Can't init pegasospci io tag");
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sc->sc_memt.pbs_flags = _BUS_SPACE_LITTLE_ENDIAN|_BUS_SPACE_MEM_TYPE;
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sc->sc_memt.pbs_base = 0x00000000;
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if (ofwoea_map_space(RANGE_TYPE_PCI, RANGE_MEM, node, &sc->sc_memt,
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"pegasospci mem-space") != 0)
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panic("Can't init pegasospci mem tag");
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/* are we the primary pci bus? */
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if (of_find_firstchild_byname(OF_finddevice("/"), "pci") ==
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ca->ca_node) {
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isprim++;
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/* yes we are, now do we have an ISA child? */
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if (of_find_firstchild_byname(ca->ca_node, "isa") != -1) {
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/* The Pegasos is very simple. isa == pci */
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genppc_isa_io_space_tag = sc->sc_iot;
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genppc_isa_mem_space_tag = sc->sc_memt;
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map_isa_ioregs();
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}
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/* If we are, regarless of isa above, now we wire up interrupt
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* controllers. We had to wait because of ISA.
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*/
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ofppc_setup_pics();
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}
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pegasospci_get_chipset_tag(pc);
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pc->pc_node = node;
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pc->pc_bus = busrange[0];
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pc->pc_iot = &sc->sc_iot;
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pc->pc_memt = &sc->sc_memt;
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/* XXX Warning, the mapiodevs will go away if this region is later
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* bus space initted or mapped
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*/
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if (isprim) {
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/* Pegasos2: primary PCI host (33MHz) @ 0x80000000 */
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pc->pc_addr = mapiodev(PEGASOS2_PCI0_ADDR, 4);
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pc->pc_data = mapiodev(PEGASOS2_PCI0_DATA, 4);
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} else {
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/* Pegasos2: second PCI host (66MHz) @ 0xc0000000 */
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pc->pc_addr = mapiodev(PEGASOS2_PCI1_ADDR, 4);
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pc->pc_data = mapiodev(PEGASOS2_PCI1_DATA, 4);
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pciagp_magic = mapiodev(PEGASOS2_AGP_MAGIC, 8);
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pc->pc_conf_read = pegasospci_indirect_conf_read;
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pc->pc_conf_write = pegasospci_indirect_conf_write;
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}
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pbi = malloc(sizeof(struct genppc_pci_chipset_businfo),
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M_DEVBUF, M_NOWAIT);
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KASSERT(pbi != NULL);
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pbi->pbi_properties = prop_dictionary_create();
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KASSERT(pbi->pbi_properties != NULL);
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SIMPLEQ_INIT(&pc->pc_pbi);
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SIMPLEQ_INSERT_TAIL(&pc->pc_pbi, pbi, next);
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genofw_setup_pciintr_map((void *)pc, pbi, pc->pc_node);
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memset(&pba, 0, sizeof(pba));
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pba.pba_memt = pc->pc_memt;
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pba.pba_iot = pc->pc_iot;
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pba.pba_dmat = &pci_bus_dma_tag;
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pba.pba_dmat64 = NULL;
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pba.pba_bus = pc->pc_bus;
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pba.pba_bridgetag = NULL;
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pba.pba_pc = pc;
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pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED;
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config_found_ia(self, "pcibus", &pba, pcibusprint);
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}
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static pcireg_t
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pegasospci_indirect_conf_read(void *cookie, pcitag_t tag, int reg)
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{
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pci_chipset_tag_t pc = cookie;
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pcireg_t data;
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int s;
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s = splhigh();
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out32rb(pciagp_magic, PEGASOS2_AGP_MAGIC_COOKIE);
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out32rb(pc->pc_addr, tag | reg);
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data = in32rb(pc->pc_data);
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out32rb(pc->pc_addr, 0);
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out32rb(pciagp_magic + 1, PEGASOS2_AGP_MAGIC_COOKIE);
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splx(s);
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return data;
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}
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static void
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pegasospci_indirect_conf_write(void *cookie, pcitag_t tag, int reg,
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pcireg_t data)
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{
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pci_chipset_tag_t pc = cookie;
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int s;
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s = splhigh();
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out32rb(pciagp_magic, PEGASOS2_AGP_MAGIC_COOKIE);
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out32rb(pc->pc_addr, tag | reg);
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out32rb(pc->pc_data, data);
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out32rb(pc->pc_addr, 0);
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out32rb(pciagp_magic + 1, PEGASOS2_AGP_MAGIC_COOKIE);
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splx(s);
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}
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