0fb6b9a8f8
Rather than an "iointr" routine that decomposes a vector into an IRQ, we maintain a vector table directly, hooking up each "iointr" routine at the correct vector. This also allows us to hook device interrupts up to specific vectors (c.f. Jensen). We can shave even more cycles off, here, and I will, but it requires some changes to the alpha_shared_intr stuff.
410 lines
11 KiB
C
410 lines
11 KiB
C
/* $NetBSD: pci_eb164.c,v 1.30 2001/07/27 00:25:20 thorpej Exp $ */
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/*-
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* Copyright (c) 1998 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
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* NASA Ames Research Center.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 1995, 1996 Carnegie-Mellon University.
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* All rights reserved.
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*
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* Author: Chris G. Demetriou
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*
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* Permission to use, copy, modify and distribute this software and
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* its documentation is hereby granted, provided that both the copyright
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* notice and this permission notice appear in all copies of the
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* software, derivative works or modified versions, and any portions
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* thereof, and that both notices appear in supporting documentation.
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*
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* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
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* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
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* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*
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* Carnegie Mellon requests users of this software to return to
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*
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* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
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* School of Computer Science
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* Carnegie Mellon University
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* Pittsburgh PA 15213-3890
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*
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* any improvements or extensions that they make and grant Carnegie the
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* rights to redistribute these changes.
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*/
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#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
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__KERNEL_RCSID(0, "$NetBSD: pci_eb164.c,v 1.30 2001/07/27 00:25:20 thorpej Exp $");
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#include <sys/types.h>
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#include <sys/param.h>
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#include <sys/time.h>
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#include <sys/systm.h>
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#include <sys/errno.h>
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#include <sys/malloc.h>
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#include <sys/device.h>
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#include <sys/syslog.h>
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#include <uvm/uvm_extern.h>
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#include <machine/autoconf.h>
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#include <machine/rpb.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pciidereg.h>
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#include <dev/pci/pciidevar.h>
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#include <alpha/pci/ciareg.h>
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#include <alpha/pci/ciavar.h>
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#include <alpha/pci/pci_eb164.h>
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#include "sio.h"
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#if NSIO
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#include <alpha/pci/siovar.h>
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#endif
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int dec_eb164_intr_map __P((struct pci_attach_args *, pci_intr_handle_t *));
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const char *dec_eb164_intr_string __P((void *, pci_intr_handle_t));
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const struct evcnt *dec_eb164_intr_evcnt __P((void *, pci_intr_handle_t));
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void *dec_eb164_intr_establish __P((void *, pci_intr_handle_t,
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int, int (*func)(void *), void *));
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void dec_eb164_intr_disestablish __P((void *, void *));
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void *dec_eb164_pciide_compat_intr_establish __P((void *, struct device *,
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struct pci_attach_args *, int, int (*)(void *), void *));
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#define EB164_SIO_IRQ 4
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#define EB164_MAX_IRQ 24
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#define PCI_STRAY_MAX 5
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struct alpha_shared_intr *eb164_pci_intr;
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bus_space_tag_t eb164_intrgate_iot;
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bus_space_handle_t eb164_intrgate_ioh;
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void eb164_iointr __P((void *arg, unsigned long vec));
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extern void eb164_intr_enable __P((int irq)); /* pci_eb164_intr.S */
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extern void eb164_intr_disable __P((int irq)); /* pci_eb164_intr.S */
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void
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pci_eb164_pickintr(ccp)
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struct cia_config *ccp;
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{
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bus_space_tag_t iot = &ccp->cc_iot;
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pci_chipset_tag_t pc = &ccp->cc_pc;
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char *cp;
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int i;
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pc->pc_intr_v = ccp;
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pc->pc_intr_map = dec_eb164_intr_map;
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pc->pc_intr_string = dec_eb164_intr_string;
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pc->pc_intr_evcnt = dec_eb164_intr_evcnt;
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pc->pc_intr_establish = dec_eb164_intr_establish;
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pc->pc_intr_disestablish = dec_eb164_intr_disestablish;
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pc->pc_pciide_compat_intr_establish =
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dec_eb164_pciide_compat_intr_establish;
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eb164_intrgate_iot = iot;
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if (bus_space_map(eb164_intrgate_iot, 0x804, 3, 0,
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&eb164_intrgate_ioh) != 0)
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panic("pci_eb164_pickintr: couldn't map interrupt PLD");
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for (i = 0; i < EB164_MAX_IRQ; i++)
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eb164_intr_disable(i);
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eb164_pci_intr = alpha_shared_intr_alloc(EB164_MAX_IRQ, 8);
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for (i = 0; i < EB164_MAX_IRQ; i++) {
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/*
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* Systems with a Pyxis seem to have problems with
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* stray interrupts, so just ignore them. Sigh,
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* I hate buggy hardware.
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*/
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alpha_shared_intr_set_maxstrays(eb164_pci_intr, i,
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(ccp->cc_flags & CCF_ISPYXIS) ? 0 : PCI_STRAY_MAX);
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cp = alpha_shared_intr_string(eb164_pci_intr, i);
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sprintf(cp, "irq %d", i);
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evcnt_attach_dynamic(alpha_shared_intr_evcnt(
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eb164_pci_intr, i), EVCNT_TYPE_INTR, NULL,
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"eb164", cp);
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}
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#if NSIO
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sio_intr_setup(pc, iot);
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eb164_intr_enable(EB164_SIO_IRQ);
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#endif
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}
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int
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dec_eb164_intr_map(pa, ihp)
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struct pci_attach_args *pa;
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pci_intr_handle_t *ihp;
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{
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pcitag_t bustag = pa->pa_intrtag;
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int buspin = pa->pa_intrpin, line = pa->pa_intrline;
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pci_chipset_tag_t pc = pa->pa_pc;
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int bus, device, function;
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u_int64_t variation;
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if (buspin == 0) {
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/* No IRQ used. */
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return 1;
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}
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if (buspin > 4) {
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printf("dec_eb164_intr_map: bad interrupt pin %d\n", buspin);
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return 1;
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}
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alpha_pci_decompose_tag(pc, bustag, &bus, &device, &function);
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variation = hwrpb->rpb_variation & SV_ST_MASK;
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/*
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*
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* The AlphaPC 164 and AlphaPC 164LX have a CMD PCI IDE controller
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* at bus 0 device 11. These are wired to compatibility mode,
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* so do not map their interrupts.
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*
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* The AlphaPC 164SX has PCI IDE on functions 1 and 2 of the
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* Cypress PCI-ISA bridge at bus 0 device 8. These, too, are
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* wired to compatibility mode.
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*
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* Real EB164s have ISA IDE on the Super I/O chip.
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*/
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if (bus == 0) {
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if (variation >= SV_ST_ALPHAPC164_366 &&
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variation <= SV_ST_ALPHAPC164LX_600) {
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if (device == 8)
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panic("dec_eb164_intr_map: SIO device");
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if (device == 11)
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return (1);
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} else if (variation >= SV_ST_ALPHAPC164SX_400 &&
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variation <= SV_ST_ALPHAPC164SX_600) {
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if (device == 8) {
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if (function == 0)
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panic("dec_eb164_intr_map: SIO device");
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return (1);
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}
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} else {
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if (device == 8)
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panic("dec_eb164_intr_map: SIO device");
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}
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}
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/*
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* The console places the interrupt mapping in the "line" value.
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* A value of (char)-1 indicates there is no mapping.
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*/
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if (line == 0xff) {
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printf("dec_eb164_intr_map: no mapping for %d/%d/%d\n",
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bus, device, function);
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return (1);
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}
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if (line > EB164_MAX_IRQ)
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panic("dec_eb164_intr_map: eb164 irq too large (%d)\n",
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line);
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*ihp = line;
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return (0);
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}
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const char *
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dec_eb164_intr_string(ccv, ih)
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void *ccv;
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pci_intr_handle_t ih;
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{
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#if 0
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struct cia_config *ccp = ccv;
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#endif
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static char irqstr[15]; /* 11 + 2 + NULL + sanity */
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if (ih > EB164_MAX_IRQ)
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panic("dec_eb164_intr_string: bogus eb164 IRQ 0x%lx\n", ih);
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sprintf(irqstr, "eb164 irq %ld", ih);
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return (irqstr);
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}
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const struct evcnt *
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dec_eb164_intr_evcnt(ccv, ih)
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void *ccv;
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pci_intr_handle_t ih;
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{
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#if 0
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struct cia_config *ccp = ccv;
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#endif
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if (ih > EB164_MAX_IRQ)
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panic("dec_eb164_intr_string: bogus eb164 IRQ 0x%lx\n", ih);
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return (alpha_shared_intr_evcnt(eb164_pci_intr, ih));
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}
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void *
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dec_eb164_intr_establish(ccv, ih, level, func, arg)
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void *ccv, *arg;
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pci_intr_handle_t ih;
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int level;
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int (*func) __P((void *));
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{
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#if 0
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struct cia_config *ccp = ccv;
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#endif
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void *cookie;
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if (ih > EB164_MAX_IRQ)
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panic("dec_eb164_intr_establish: bogus eb164 IRQ 0x%lx\n", ih);
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cookie = alpha_shared_intr_establish(eb164_pci_intr, ih, IST_LEVEL,
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level, func, arg, "eb164 irq");
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if (cookie != NULL &&
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alpha_shared_intr_firstactive(eb164_pci_intr, ih)) {
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scb_set(0x900 + SCB_IDXTOVEC(ih), eb164_iointr, NULL);
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eb164_intr_enable(ih);
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}
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return (cookie);
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}
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void
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dec_eb164_intr_disestablish(ccv, cookie)
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void *ccv, *cookie;
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{
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#if 0
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struct cia_config *ccp = ccv;
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#endif
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struct alpha_shared_intrhand *ih = cookie;
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unsigned int irq = ih->ih_num;
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int s;
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s = splhigh();
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alpha_shared_intr_disestablish(eb164_pci_intr, cookie,
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"eb164 irq");
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if (alpha_shared_intr_isactive(eb164_pci_intr, irq) == 0) {
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eb164_intr_disable(irq);
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alpha_shared_intr_set_dfltsharetype(eb164_pci_intr, irq,
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IST_NONE);
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scb_free(0x900 + SCB_IDXTOVEC(irq));
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}
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splx(s);
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}
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void *
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dec_eb164_pciide_compat_intr_establish(v, dev, pa, chan, func, arg)
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void *v;
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struct device *dev;
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struct pci_attach_args *pa;
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int chan;
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int (*func) __P((void *));
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void *arg;
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{
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pci_chipset_tag_t pc = pa->pa_pc;
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void *cookie = NULL;
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int bus, irq;
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alpha_pci_decompose_tag(pc, pa->pa_tag, &bus, NULL, NULL);
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/*
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* If this isn't PCI bus #0, all bets are off.
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*/
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if (bus != 0)
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return (NULL);
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irq = PCIIDE_COMPAT_IRQ(chan);
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#if NSIO
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cookie = sio_intr_establish(NULL /*XXX*/, irq, IST_EDGE, IPL_BIO,
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func, arg);
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if (cookie == NULL)
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return (NULL);
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printf("%s: %s channel interrupting at %s\n", dev->dv_xname,
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PCIIDE_CHANNEL_NAME(chan), sio_intr_string(NULL /*XXX*/, irq));
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#endif
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return (cookie);
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}
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void
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eb164_iointr(arg, vec)
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void *arg;
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unsigned long vec;
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{
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int irq;
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irq = SCB_VECTOIDX(vec - 0x900);
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if (!alpha_shared_intr_dispatch(eb164_pci_intr, irq)) {
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alpha_shared_intr_stray(eb164_pci_intr, irq,
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"eb164 irq");
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if (ALPHA_SHARED_INTR_DISABLE(eb164_pci_intr, irq))
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eb164_intr_disable(irq);
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}
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}
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#if 0 /* THIS DOES NOT WORK! see pci_eb164_intr.S. */
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u_int8_t eb164_intr_mask[3] = { 0xff, 0xff, 0xff };
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void
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eb164_intr_enable(irq)
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int irq;
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{
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int byte = (irq / 8), bit = (irq % 8);
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#if 1
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printf("eb164_intr_enable: enabling %d (%d:%d)\n", irq, byte, bit);
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#endif
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eb164_intr_mask[byte] &= ~(1 << bit);
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bus_space_write_1(eb164_intrgate_iot, eb164_intrgate_ioh, byte,
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eb164_intr_mask[byte]);
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}
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void
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eb164_intr_disable(irq)
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int irq;
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{
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int byte = (irq / 8), bit = (irq % 8);
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#if 1
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printf("eb164_intr_disable: disabling %d (%d:%d)\n", irq, byte, bit);
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#endif
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eb164_intr_mask[byte] |= (1 << bit);
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bus_space_write_1(eb164_intrgate_iot, eb164_intrgate_ioh, byte,
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eb164_intr_mask[byte]);
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}
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#endif
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