360 lines
16 KiB
C
360 lines
16 KiB
C
/* $NetBSD: gtmpscreg.h,v 1.4 2010/04/28 13:51:56 kiyohara Exp $ */
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/*
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* Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Allegro Networks, Inc., and Wasabi Systems, Inc.
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* 4. The name of Allegro Networks, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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* 5. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY ALLEGRO NETWORKS, INC. AND
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* WASABI SYSTEMS, INC. ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
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* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
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* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL EITHER ALLEGRO NETWORKS, INC. OR WASABI SYSTEMS, INC.
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* gtmpscreg.h - register defines for GT-64260 MPSC
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*
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* creation Sun Apr 8 11:49:57 PDT 2001 cliff
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*/
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#ifndef _GTMPSCREG_H
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#define _GTMPSCREG_H
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#ifndef BIT
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#define BIT(bitno) (1U << (bitno))
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#endif
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#ifndef BITS
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#define BITS(hi, lo) ((~((~0) << ((hi) + 1))) & ((~0) << (lo)))
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#endif
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#define GTMPSC_BASE(u) (MPSC0_BASE + ((u) << 12))
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#define GTMPSC_SIZE 0x1000
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#define GTMPSC_NCHAN 2 /* Number of MPSC channels */
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/*******************************************************************************
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*
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* MPSC register address offsets relative to the base mapping
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*/
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#define GTMPSC_MMCR_LO 0x000 /* MPSC Main Config Register Low */
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#define GTMPSC_MMCR_HI 0x004 /* MPSC Main Config Register High */
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#define GTMPSC_MPCR 0x008 /* MPSC Protocol Config Register */
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#define GTMPSC_CHR_BASE 0x008 /* MPSC Channel Register Base */
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#define GTMPSC_CHRN(n) (GTMPSC_CHR_BASE + ((n) << 2))
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#define GTMPSC_NCHR 11 /* CHR 1-11? */
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#define GTMPSC_MRR 0xb400 /* MPSC Routing Register */
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#define GTMPSC_RCRR 0xb404 /* MPSC RX Clock Routing Register */
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#define GTMPSC_TCRR 0xb408 /* MPSC TX Clock Routing Register */
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/*******************************************************************************
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*
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* MPSC register values & bit defines
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*
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* values are provided for UART mode only
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*/
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/*
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* MPSC Routing Register bits
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*/
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#define GTMPSC_MRR_PORT0 0 /* serial port #0 */
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#define GTMPSC_MRR_NONE 7 /* unconnected */
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/* all other "routes" resvd. */
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#define GTMPSC_MRR_MR0_MASK BITS(2,0) /* routing mask for MPSC0 */
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#define GTMPSC_MRR_RESa BITS(5,3)
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#define GTMPSC_MRR_MR1_MASK BITS(8,6) /* routing mask for MPSC1 */
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#define GTMPSC_MRR_RESb BITS(30,9)
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#define GTMPSC_MRRE_DSC BIT(31) /* "Don't Stop Clock" */
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#define GTMPSC_MRR_RES (GTMPSC_MRR_RESa|GTMPSC_MRR_RESb)
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/*
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* MPSC Clock Routing Register bits
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* the bitfields and route definitions are common for RCRR and TCRR
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* except for MPSC_TCRR_TSCLK0
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*/
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#define GTMPSC_CRR_BRG0 0x0 /* Baud Rate Generator #0 */
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#define GTMPSC_CRR_BRG1 0x1 /* Baud Rate Generator #1 */
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#define GTMPSC_CRR_BRG2 0x2 /* Baud Rate Generator #2 */
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#define GTMPSC_CRR_SCLK0 0x8 /* SCLK0 */
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#define GTMPSC_TCRR_TSCLK0 0x9 /* TSCLK0 (for TCRR only) */
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/* all other values resvd. */
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#define GTMPSC_CRR(u, v) ((v) << GTMPSC_CRR_SHIFT(u))
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#define GTMPSC_CRR_SHIFT(u) ((u) * 8)
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#define GTMPSC_CRR_MASK 0xf
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#define GTMPSC_CRR_RESa BITS(7,4)
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#define GTMPSC_CRR_RESb BITS(31,12)
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#define GTMPSC_CRR_RES (GTMPSC_CRR_RESa|GTMPSC_CRR_RESb)
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/*
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* MPSC Main Configuration Register LO bits
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*/
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#define GTMPSC_MMCR_LO_MODE_MASK BITS(2,0)
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#define GTMPSC_MMCR_LO_MODE_UART (0x4 << 0) /* UART mode */
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#define GTMPSC_MMCR_LO_TTX BIT(3) /* Transparent TX */
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#define GTMPSC_MMCR_LO_TRX BIT(4) /* Transparent RX */
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#define GTMPSC_MMCR_LO_RESa BIT(5)
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#define GTMPSC_MMCR_LO_ET BIT(6) /* Enable TX */
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#define GTMPSC_MMCR_LO_ER BIT(7) /* Enable RX */
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#define GTMPSC_MMCR_LO_LPBK_MASK BITS(9,8) /* Loop Back */
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#define GTMPSC_MMCR_LO_LPBK_NONE (0 << 8) /* Normal (non-loop) */
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#define GTMPSC_MMCR_LO_LPBK_LOOP (1 << 8) /* Loop Back */
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#define GTMPSC_MMCR_LO_LPBK_ECHO (2 << 8) /* Echo */
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#define GTMPSC_MMCR_LO_LPBK_LBE (3 << 8) /* Loop Back and Echo */
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#define GTMPSC_MMCR_LO_NLM BIT(10) /* Null Modem */
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#define GTMPSC_MMCR_LO_RESb BIT(11)
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#define GTMPSC_MMCR_LO_TSYN BIT(12) /* Transmitter sync to Rcvr. */
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#define GTMPSC_MMCR_LO_RESc BIT(13)
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#define GTMPSC_MMCR_LO_TSNS_MASK BITS(15,14) /* Transmit Sense */
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#define GTMPSC_MMCR_LO_TSNS_INF (0 << 14) /* Infinite */
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#define GTMPSC_MMCR_LO_TIDL BIT(16) /* TX Idles */
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#define GTMPSC_MMCR_LO_RTSM BIT(17) /* RTS Mode */
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#define GTMPSC_MMCR_LO_RESd BIT(18)
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#define GTMPSC_MMCR_LO_CTSS BIT(19) /* CTS Sampling mode */
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#define GTMPSC_MMCR_LO_CDS BIT(20) /* CD Sampling mode */
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#define GTMPSC_MMCR_LO_CTSM BIT(21) /* CTS operating Mode */
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#define GTMPSC_MMCR_LO_CDM BIT(22) /* CD operating Mode */
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#define GTMPSC_MMCR_LO_CRCM_MASK BITS(25,23) /* CRC Mode */
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#define GTMPSC_MMCR_LO_CRCM_NONE (0 << 23) /* CRC Mode */
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#define GTMPSC_MMCR_LO_RESe BITS(27,26)
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#define GTMPSC_MMCR_LO_TRVD BIT(28) /* Transmit Reverse Data */
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#define GTMPSC_MMCR_LO_RRVD BIT(29) /* Receive Reverse Data */
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#define GTMPSC_MMCR_LO_RESf BIT(30)
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#define GTMPSC_MMCR_LO_GDE BIT(31) /* Glitch Detect Enable */
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#define GTMPSC_MMCR_LO_RES \
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(GTMPSC_MMCR_LO_RESa|GTMPSC_MMCR_LO_RESb|GTMPSC_MMCR_LO_RESc \
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|GTMPSC_MMCR_LO_RESd|GTMPSC_MMCR_LO_RESe|GTMPSC_MMCR_LO_RESf)
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/*
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* MPSC Main Configuration Register HI bits
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*/
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#define GTMPSC_MMCR_HI_TCI BIT(0) /* TX Clock Invert */
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#define GTMPSC_MMCR_HI_TINV BIT(1) /* TX Bitstream Inversion */
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#define GTMPSC_MMCR_HI_TPL BITS(4,2) /* TX Preable Length */
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#define GTMPSC_MMCR_HI_TPL_NONE 0 /* no TX Preable (default) */
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#define GTMPSC_MMCR_HI_TPL_16 (6 << 2) /* 16 byte preamble */
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#define GTMPSC_MMCR_HI_TPPT_MASK BITS(8,5) /* TX Preable Pattern */
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#define GTMPSC_MMCR_HI_TPPT_NONE (0 << 5) /* TX Preable Pattern */
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#define GTMPSC_MMCR_HI_TCDV_MASK BITS(10,9) /* TX Clock Divide */
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#define GTMPSC_MMCR_HI_TCDV_1X (0 << 9) /* 1x clock mode */
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#define GTMPSC_MMCR_HI_TCDV_8X (1 << 9) /* 8x clock mode */
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#define GTMPSC_MMCR_HI_TCDV_16X (2 << 9) /* 16x clock mode */
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#define GTMPSC_MMCR_HI_TCDV_32X (3 << 9) /* 32x clock mode */
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#define GTMPSC_MMCR_HI_TDEC_MASK BITS(13,11) /* TX Encoder */
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#define GTMPSC_MMCR_HI_TDEC_NRZ (0 << 9) /* NRZ (default) */
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#define GTMPSC_MMCR_HI_TDEC_NRZI (1 << 9) /* NRZI (mark) */
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#define GTMPSC_MMCR_HI_TDEC_FM0 (2 << 9) /* FM0 */
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#define GTMPSC_MMCR_HI_TDEC_MAN (4 << 9) /* Manchester */
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#define GTMPSC_MMCR_HI_TDEC_DMAN (6 << 9) /* Differential Manchester */
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/* all other values rsvd. */
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#define GTMPSC_MMCR_HI_RESa BITS(15,14)
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#define GTMPSC_MMCR_HI_RINV BIT(16) /* RX Bitstream Inversion */
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#define GTMPSC_MMCR_HI_GDW BITS(20,17) /* Clock Glitch Width */
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#define GTMPSC_MMCR_HI_RESb BIT(21)
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#define GTMPSC_MMCR_HI_RDW BIT(22) /* Reveive Data Width */
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#define GTMPSC_MMCR_HI_RSYL_MASK BITS(24,23) /* Reveive Sync Width */
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#define GTMPSC_MMCR_HI_RSYL_EXT (0 << 23) /* External sync */
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#define GTMPSC_MMCR_HI_RSYL_4BIT (1 << 23) /* 4-bit sync */
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#define GTMPSC_MMCR_HI_RSYL_8BIT (2 << 23) /* 8-bit sync */
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#define GTMPSC_MMCR_HI_RSYL_16BIT (3 << 23) /* 16-bit sync */
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#define GTMPSC_MMCR_HI_RCDV_MASK BITS(26,25) /* Receive Clock Divider */
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#define GTMPSC_MMCR_HI_RCDV_1X (0 << 25) /* 1x clock mode (default) */
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#define GTMPSC_MMCR_HI_RCDV_8X (1 << 25) /* 8x clock mode (default) */
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#define GTMPSC_MMCR_HI_RCDV_16X (2 << 25) /* 16x clock mode (default) */
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#define GTMPSC_MMCR_HI_RCDV_32X (3 << 25) /* 16x clock mode (default) */
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#define GTMPSC_MMCR_HI_RENC_MASK BITS(29,27) /* Receive Encoder */
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#define GTMPSC_MMCR_HI_RENC_NRZ (0 << 27) /* NRZ (default) */
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#define GTMPSC_MMCR_HI_RENC_NRZI (1 << 27) /* NRZI */
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#define GTMPSC_MMCR_HI_RENC_FM0 (2 << 27) /* FM0 */
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#define GTMPSC_MMCR_HI_RENC_MAN (4 << 27) /* Manchester */
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#define GTMPSC_MMCR_HI_RENC_DMAN (6 << 27) /* Differential Manchester */
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/* all other values rsvd. */
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#define GTMPSC_MMCR_HI_SEDG_MASK BITS(31,30) /* Sync Clock Edge */
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#define GTMPSC_MMCR_HI_SEDG_BOTH (0 << 30) /* rising and falling (dflt) */
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#define GTMPSC_MMCR_HI_SEDG_RISE (1 << 30) /* rising edge */
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#define GTMPSC_MMCR_HI_SEDG_FALL (2 << 30) /* falling edge */
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#define GTMPSC_MMCR_HI_SEDG_NONE (3 << 30) /* no adjustment */
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/*
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* SDMAx Command/Status Register bits for UART Mode, RX
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*
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* XXX these belong in sdmareg.h ?
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*/
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#define SDMA_CSR_RX_PE BIT(0) /* Parity Error */
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#define SDMA_CSR_RX_CDL BIT(1) /* Carrier Detect Loss */
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#define SDMA_CSR_RX_RESa BIT(2)
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#define SDMA_CSR_RX_FR BIT(3) /* Framing Error */
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#define SDMA_CSR_RX_RESb BITS(5,4)
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#define SDMA_CSR_RX_OR BIT(6) /* Data Overrun */
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#define SDMA_CSR_RX_RESc BITS(8,7)
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#define SDMA_CSR_RX_BR BIT(9) /* Break Received */
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#define SDMA_CSR_RX_MI BIT(10) /* Max Idle */
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#define SDMA_CSR_RX_ADDR BIT(11) /* Address */
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#define SDMA_CSR_RX_AMATCH BIT(12) /* Address match */
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#define SDMA_CSR_RX_CT BIT(13) /* Transparency Control char */
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#define SDMA_CSR_RX_C BIT(14) /* Control char */
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#define SDMA_CSR_RX_ES BIT(15) /* Error Summary */
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#define SDMA_CSR_RX_L BIT(16) /* Last */
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#define SDMA_CSR_RX_F BIT(17) /* First */
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#define SDMA_CSR_RX_RESd BITS(22,18)
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#define SDMA_CSR_RX_EI BIT(23) /* Enable Interrupt */
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#define SDMA_CSR_RX_RESe BITS(29,24)
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#define SDMA_CSR_RX_AUTO BIT(30) /* Auto Mode */
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#define SDMA_CSR_RX_OWN BIT(31) /* Owner */
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#define SDMA_CSR_RX_RES (SDMA_CSR_RX_RESa|SDMA_CSR_RX_RESb|SDMA_CSR_RX_RESc \
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|SDMA_CSR_RX_RESd|SDMA_CSR_RX_RESe)
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/*
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* SDMAx Command/Status Register bits for UART Mode, TX
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*/
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#define SDMA_CSR_TX_RESa BIT(0)
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#define SDMA_CSR_TX_CTSL BIT(1) /* CTS Loss */
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#define SDMA_CSR_TX_RESb BITS(14,2)
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#define SDMA_CSR_TX_ES BIT(15) /* Error Summary */
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#define SDMA_CSR_TX_L BIT(16) /* Last */
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#define SDMA_CSR_TX_F BIT(17) /* First */
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#define SDMA_CSR_TX_P BIT(18) /* Preamble */
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#define SDMA_CSR_TX_ADDR BIT(19) /* Address */
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#define SDMA_CSR_TX_NS BIT(20) /* No Stop Bit */
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#define SDMA_CSR_TX_RESc BITS(22,21)
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#define SDMA_CSR_TX_EI BIT(23) /* Enable Interrupt */
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#define SDMA_CSR_TX_RESd BITS(29,24)
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#define SDMA_CSR_TX_AUTO BIT(30) /* Auto Mode */
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#define SDMA_CSR_TX_OWN BIT(31) /* Owner */
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#define SDMA_CSR_TX_RES \
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(SDMA_CSR_TX_RESa|SDMA_CSR_TX_RESb|SDMA_CSR_TX_RESc|SDMA_CSR_TX_RESd)
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/*
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* MPSCx Protocol Configuration Register for UART Mode
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*/
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#define GTMPSC_MPCR_RESa BITS(5,0)
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#define GTMPSC_MPCR_DRT BIT(6) /* Disable Rx on Tx */
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#define GTMPSC_MPCR_ISO BIT(7) /* Isochronous Mode */
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#define GTMPSC_MPCR_RZS BIT(8) /* Rx Zero Stop Bit(s) */
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#define GTMPSC_MPCR_FRZ BIT(9) /* Freeze Tx */
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#define GTMPSC_MPCR_UM_MASK BITS(11,10) /* UART Mode mask */
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#define GTMPSC_MPCR_UM_NORM (0 << 10) /* Normal UART Mode */
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#define GTMPSC_MPCR_UM_MDROP (1 << 10) /* Multi-Drop UART Mode */
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/* other values are resvd. */
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#define GTMPSC_MPCR_CLMASK BITS(13,12) /* Character Length mask */
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#define GTMPSC_MPCR_CL_5 (0 << 12) /* 5 data bits */
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#define GTMPSC_MPCR_CL_6 (1 << 12) /* 6 data bits */
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#define GTMPSC_MPCR_CL_7 (2 << 12) /* 7 data bits */
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#define GTMPSC_MPCR_CL_8 (3 << 12) /* 8 data bits */
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#define GTMPSC_MPCR_SBL_1 (0 << 14) /* 1 stop bit */
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#define GTMPSC_MPCR_SBL_2 (1 << 14) /* 2 stop bits */
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#define GTMPSC_MPCR_FLC_NORM 0x0 /* Normal Flow Ctl mode */
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#define GTMPSC_MPCR_FLC_ASYNC BIT(15) /* Asynchronous Flow Ctl mode */
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#define GTMPSC_MPCR_RESb BITS(31,16)
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#define GTMPSC_MPCR_RES (GTMPSC_MPCR_RESa|GTMPSC_MPCR_RESb)
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/*
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* MPSC Channel Register 1 for UART Mode "Break/Stuff"
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*/
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#define GTMPSC_CHR1_TCS BITS(7,0) /* Constrol Stuff Character */
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#define GTMPSC_CHR1_BRK BITS(23,16) /* Break Count */
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#define GTMPSC_CHR1_RES BITS(15,8)|BITS(31,24)
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/*
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* MPSC Channel Register 2 for UART Mode "Command"
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*/
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#define GTMPSC_CHR2_RESa BIT(0)
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#define GTMPSC_CHR2_TEV BIT(1) /* Tx Enb. Vert. Redundancy */
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#define GTMPSC_CHR2_TPM_MASK BITS(3,2) /* Tx Parity Mode mask */
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#define GTMPSC_CHR2_TPM_ODD (0 << 2) /* Odd Tx Parity */
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#define GTMPSC_CHR2_TPM_LOW (1 << 2) /* Low (always 0) Tx Parity */
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#define GTMPSC_CHR2_TPM_EVEN (2 << 2) /* Even Tx Parity */
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#define GTMPSC_CHR2_TPM_HIGH (3 << 2) /* High (always 1) Tx Parity */
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#define GTMPSC_CHR2_RESb BITS(6,4)
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#define GTMPSC_CHR2_TXABORT BIT(7) /* Tx Abort */
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#define GTMPSC_CHR2_RESc BIT(8)
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#define GTMPSC_CHR2_TCS BIT(9) /* Tx TCS Char */
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#define GTMPSC_CHR2_RESd BITS(16,10)
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#define GTMPSC_CHR2_REC BIT(17) /* Rx Enb. Vert. Redundancy */
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#define GTMPSC_CHR2_RPM_MASK BITS(19,18) /* Rx Parity Mode mask */
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#define GTMPSC_CHR2_RPM_ODD (0 << 18) /* Odd Rx Parity */
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#define GTMPSC_CHR2_RPM_LOW (1 << 18) /* Low (always 0) Rx Parity */
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#define GTMPSC_CHR2_RPM_EVEN (2 << 18) /* Even Rx Parity */
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#define GTMPSC_CHR2_RPM_HIGH (3 << 18) /* High (always 1) Rx Parity */
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#define GTMPSC_CHR2_RESe BITS(22,20)
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#define GTMPSC_CHR2_RXABORT BIT(23) /* Rx Abort */
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#define GTMPSC_CHR2_RESf BIT(24)
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#define GTMPSC_CHR2_CRD BIT(25) /* Close RX Descriptor */
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#define GTMPSC_CHR2_RESg BITS(30,26)
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#define GTMPSC_CHR2_EH BIT(31) /* Enter Hunt */
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#define GTMPSC_CHR2_RES \
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(GTMPSC_CHR2_RESa|GTMPSC_CHR2_RESb|GTMPSC_CHR2_RESc| \
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GTMPSC_CHR2_RESd|GTMPSC_CHR2_RESe|GTMPSC_CHR2_RESf| \
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GTMPSC_CHR2_RESg)
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/*
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* MPSC Channel Register 3 for UART Mode "Max Idle"
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*/
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#define GTMPSC_CHR3_MIR BITS(15,0) /* Max Idle Char count */
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#define GTMPSC_CHR3_RES BITS(31,16)
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/*
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* MPSC Channel Register 4 for UART Mode "Control Filtering"
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*/
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#define GTMPSC_CHR4_CFR BITS(7,0) /* Control bit compare enable */
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#define GTMPSC_CHR4_RES BITS(31,8)
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/*
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* MPSC Channel Registers 5..8 for UART Mode "UART Control Character"
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*
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* NOTE: two 16 bit CHRCC fields exist in each of Channel Registers 5..8
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*/
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#define GTMPSC_CHRCC_SHIFT 16
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#define GTMPSC_CHRCC_CHAR BITS(7,0) /* the control character */
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#define GTMPSC_CHRCC_RES BITS(11,8)
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#define GTMPSC_CHRCC_INT BIT(12) /* Interrupt */
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#define GTMPSC_CHRCC_CO BIT(13) /* ISO 3309 Control Octet */
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#define GTMPSC_CHRCC_R BIT(14) /* Reject */
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#define GTMPSC_CHRCC_V BIT(15) /* Valid */
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/*
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* MPSC Channel Register 9 for UART Mode "Address" (for multidrop operation)
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*/
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#define GTMPSC_CHR9_AD1 BITS(7,0) /* address #1 */
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#define GTMPSC_CHR9_RESa BITS(14,8)
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#define GTMPSC_CHR9_MODE1 BIT(15) /* mode #1 */
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#define GTMPSC_CHR9_AD2 BITS(23,16) /* address #2 */
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#define GTMPSC_CHR9_RESb BITS(30,24)
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#define GTMPSC_CHR9_MODE2 BIT(31) /* mode #2 */
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#define GTMPSC_CHR9_RES (GTMPSC_CHR9_RESa|GTMPSC_CHR9_RESb)
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/*
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* MPSC Channel Register 10 for UART Mode "Event Status"
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*/
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#define GTMPSC_CHR10_CTS BIT(0) /* Clear To Send */
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#define GTMPSC_CHR10_CD BIT(1) /* Carrier Detect */
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#define GTMPSC_CHR10_RESa BIT(2)
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#define GTMPSC_CHR10_TIDLE BIT(3) /* Tx in Idle State */
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#define GTMPSC_CHR10_RESb BIT(4)
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#define GTMPSC_CHR10_RHS BIT(5) /* Rx in HUNT State */
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#define GTMPSC_CHR10_RESc BIT(6)
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#define GTMPSC_CHR10_RLS BIT(7) /* Rx Line STatus */
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#define GTMPSC_CHR10_RESd BITS(10,8)
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#define GTMPSC_CHR10_RLIDL BIT(11) /* Rx IDLE Line */
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#define GTMPSC_CHR10_RESe BITS(15,12)
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#define GTMPSC_CHR10_RCRn BITS(23,16) /* Received Control Char # */
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#define GTMPSC_CHR10_RESf BITS(31,24)
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#define GTMPSC_CHR10_RES \
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(GTMPSC_CHR10_RESa|GTMPSC_CHR10_RESb|GTMPSC_CHR10_RESc \
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|GTMPSC_CHR10_RESd|GTMPSC_CHR10_RESe|GTMPSC_CHR10_RESf)
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#endif /* _GTMPSCREG_H */
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