370 lines
8.9 KiB
C
370 lines
8.9 KiB
C
/* $NetBSD: s3c2410_intr.c,v 1.11 2008/11/24 11:29:52 dogcow Exp $ */
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/*
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* Copyright (c) 2003 Genetec corporation. All rights reserved.
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* Written by Hiroyuki Bessho for Genetec corporation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of Genetec corporation may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY GENETEC CORP. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORP.
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* IRQ handler for Samsung S3C2410 processor.
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* It has integrated interrupt controller.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: s3c2410_intr.c,v 1.11 2008/11/24 11:29:52 dogcow Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/malloc.h>
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#include <uvm/uvm_extern.h>
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <arm/cpufunc.h>
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#include <arm/s3c2xx0/s3c2410reg.h>
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#include <arm/s3c2xx0/s3c2410var.h>
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/*
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* interrupt dispatch table.
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*/
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struct s3c2xx0_intr_dispatch handler[ICU_LEN];
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volatile int intr_mask;
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#ifdef __HAVE_FAST_SOFTINTS
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volatile int softint_pending;
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volatile int soft_intr_mask;
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#endif
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volatile int global_intr_mask = 0; /* mask some interrupts at all spl level */
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/* interrupt masks for each level */
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int s3c2xx0_imask[NIPL];
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int s3c2xx0_ilevel[ICU_LEN];
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#ifdef __HAVE_FAST_SOFTINTS
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int s3c24x0_soft_imask[NIPL];
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#endif
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vaddr_t intctl_base; /* interrupt controller registers */
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#define icreg(offset) \
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(*(volatile uint32_t *)(intctl_base+(offset)))
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#ifdef __HAVE_FAST_SOFTINTS
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/*
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* Map a software interrupt queue to an interrupt priority level.
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*/
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static const int si_to_ipl[] = {
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[SI_SOFTBIO] = IPL_SOFTBIO,
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[SI_SOFTCLOCK] = IPL_SOFTCLOCK,
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[SI_SOFTNET] = IPL_SOFTNET,
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[SI_SOFTSERIAL] = IPL_SOFTSERIAL,
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};
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#endif
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#define PENDING_CLEAR_MASK (~0)
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/*
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* called from irq_entry.
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*/
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void s3c2410_irq_handler(struct clockframe *);
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void
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s3c2410_irq_handler(struct clockframe *frame)
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{
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uint32_t irqbits;
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int irqno;
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int saved_spl_level;
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saved_spl_level = curcpl();
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#ifdef DIAGNOSTIC
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if (curcpu()->ci_intr_depth > 10)
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panic("nested intr too deep");
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#endif
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while ((irqbits = icreg(INTCTL_INTPND)) != 0) {
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/* Note: Only one bit in INTPND register is set */
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irqno = icreg(INTCTL_INTOFFSET);
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#ifdef DIAGNOSTIC
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if (__predict_false((irqbits & (1<<irqno)) == 0)) {
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/* This shouldn't happen */
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printf("INTOFFSET=%d, INTPND=%x\n", irqno, irqbits);
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break;
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}
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#endif
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/* raise spl to stop interrupts of lower priorities */
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if (saved_spl_level < handler[irqno].level)
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s3c2xx0_setipl(handler[irqno].level);
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/* clear pending bit */
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icreg(INTCTL_SRCPND) = PENDING_CLEAR_MASK & (1 << irqno);
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icreg(INTCTL_INTPND) = PENDING_CLEAR_MASK & (1 << irqno);
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enable_interrupts(I32_bit); /* allow nested interrupts */
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(*handler[irqno].func) (
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handler[irqno].cookie == 0
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? frame : handler[irqno].cookie);
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disable_interrupts(I32_bit);
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/* restore spl to that was when this interrupt happen */
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s3c2xx0_setipl(saved_spl_level);
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}
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#ifdef __HAVE_FAST_SOFTINTS
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cpu_dosoftints();
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#endif
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}
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/*
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* Handler for main IRQ of cascaded interrupts.
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*/
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static int
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cascade_irq_handler(void *cookie)
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{
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int index = (int)cookie - 1;
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uint32_t irqbits;
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int irqno, i;
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int save = disable_interrupts(I32_bit);
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KASSERT(0 <= index && index <= 3);
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irqbits = icreg(INTCTL_SUBSRCPND) &
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~icreg(INTCTL_INTSUBMSK) & (0x07 << (3*index));
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for (irqno = 3*index; irqbits; ++irqno) {
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if ((irqbits & (1<<irqno)) == 0)
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continue;
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/* clear pending bit */
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irqbits &= ~(1<<irqno);
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icreg(INTCTL_SUBSRCPND) = (1 << irqno);
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/* allow nested interrupts. SPL is already set
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* correctly by main handler. */
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restore_interrupts(save);
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i = S3C2410_SUBIRQ_MIN + irqno;
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(* handler[i].func)(handler[i].cookie);
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disable_interrupts(I32_bit);
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}
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return 1;
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}
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static const uint8_t subirq_to_main[] = {
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S3C2410_INT_UART0,
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S3C2410_INT_UART0,
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S3C2410_INT_UART0,
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S3C2410_INT_UART1,
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S3C2410_INT_UART1,
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S3C2410_INT_UART1,
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S3C2410_INT_UART2,
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S3C2410_INT_UART2,
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S3C2410_INT_UART2,
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S3C24X0_INT_ADCTC,
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S3C24X0_INT_ADCTC,
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};
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void *
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s3c24x0_intr_establish(int irqno, int level, int type,
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int (* func) (void *), void *cookie)
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{
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int save;
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if (irqno < 0 || irqno >= ICU_LEN ||
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type < IST_NONE || IST_EDGE_BOTH < type)
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panic("intr_establish: bogus irq or type");
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save = disable_interrupts(I32_bit);
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handler[irqno].cookie = cookie;
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handler[irqno].func = func;
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handler[irqno].level = level;
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if (irqno >= S3C2410_SUBIRQ_MIN) {
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/* cascaded interrupts. */
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int main_irqno;
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int i = (irqno - S3C2410_SUBIRQ_MIN);
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main_irqno = subirq_to_main[i];
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/* establish main irq if first time
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* be careful that cookie shouldn't be 0 */
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if (handler[main_irqno].func != cascade_irq_handler)
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s3c24x0_intr_establish(main_irqno, level, type,
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cascade_irq_handler, (void *)((i/3) + 1));
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/* unmask it in submask register */
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icreg(INTCTL_INTSUBMSK) &= ~(1<<i);
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restore_interrupts(save);
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return &handler[irqno];
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}
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s3c2xx0_update_intr_masks(irqno, level);
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/*
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* set trigger type for external interrupts 0..3
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*/
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if (irqno <= S3C24X0_INT_EXT(3)) {
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/*
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* Update external interrupt control
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*/
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s3c2410_setup_extint(irqno, type);
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}
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s3c2xx0_setipl(curcpl());
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restore_interrupts(save);
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return &handler[irqno];
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}
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static void
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init_interrupt_masks(void)
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{
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int i;
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for (i=0; i < NIPL; ++i)
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s3c2xx0_imask[i] = 0;
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#ifdef __HAVE_FAST_SOFTINTS
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s3c24x0_soft_imask[IPL_NONE] = SI_TO_IRQBIT(SI_SOFTSERIAL) |
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SI_TO_IRQBIT(SI_SOFTNET) | SI_TO_IRQBIT(SI_SOFTCLOCK) |
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SI_TO_IRQBIT(SI_SOFT);
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s3c24x0_soft_imask[IPL_SOFT] = SI_TO_IRQBIT(SI_SOFTSERIAL) |
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SI_TO_IRQBIT(SI_SOFTNET) | SI_TO_IRQBIT(SI_SOFTCLOCK);
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/*
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* splsoftclock() is the only interface that users of the
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* generic software interrupt facility have to block their
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* soft intrs, so splsoftclock() must also block IPL_SOFT.
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*/
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s3c24x0_soft_imask[IPL_SOFTCLOCK] = SI_TO_IRQBIT(SI_SOFTSERIAL) |
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SI_TO_IRQBIT(SI_SOFTNET);
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/*
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* splsoftnet() must also block splsoftclock(), since we don't
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* want timer-driven network events to occur while we're
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* processing incoming packets.
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*/
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s3c24x0_soft_imask[IPL_SOFTNET] = SI_TO_IRQBIT(SI_SOFTSERIAL);
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for (i = IPL_BIO; i < IPL_SOFTSERIAL; ++i)
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s3c24x0_soft_imask[i] = SI_TO_IRQBIT(SI_SOFTSERIAL);
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#endif
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}
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void
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s3c2410_intr_init(struct s3c24x0_softc *sc)
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{
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intctl_base = (vaddr_t) bus_space_vaddr(sc->sc_sx.sc_iot,
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sc->sc_sx.sc_intctl_ioh);
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s3c2xx0_intr_mask_reg = (uint32_t *)(intctl_base + INTCTL_INTMSK);
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/* clear all pending interrupt */
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icreg(INTCTL_SRCPND) = ~0;
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icreg(INTCTL_INTPND) = ~0;
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/* mask all sub interrupts */
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icreg(INTCTL_INTSUBMSK) = 0x7ff;
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init_interrupt_masks();
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s3c2xx0_intr_init(handler, ICU_LEN);
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}
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/*
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* mask/unmask sub interrupts
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*/
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void
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s3c2410_mask_subinterrupts(int bits)
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{
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int psw = disable_interrupts(IF32_bits);
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icreg(INTCTL_INTSUBMSK) |= bits;
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restore_interrupts(psw);
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}
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void
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s3c2410_unmask_subinterrupts(int bits)
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{
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int psw = disable_interrupts(IF32_bits);
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icreg(INTCTL_INTSUBMSK) &= ~bits;
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restore_interrupts(psw);
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}
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/*
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* Update external interrupt control
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*/
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static const u_char s3c24x0_ist[] = {
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EXTINTR_LOW, /* NONE */
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EXTINTR_FALLING, /* PULSE */
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EXTINTR_FALLING, /* EDGE */
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EXTINTR_LOW, /* LEVEL */
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EXTINTR_HIGH,
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EXTINTR_RISING,
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EXTINTR_BOTH,
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};
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void
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s3c2410_setup_extint(int extint, int type)
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{
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uint32_t reg;
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u_int trig;
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int i = extint % 8;
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int regidx = extint/8; /* GPIO_EXTINT[0:2] */
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int save;
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trig = s3c24x0_ist[type];
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save = disable_interrupts(I32_bit);
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reg = bus_space_read_4(s3c2xx0_softc->sc_iot,
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s3c2xx0_softc->sc_gpio_ioh,
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GPIO_EXTINT(regidx));
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reg = reg & ~(0x07 << (4*i));
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reg |= trig << (4*i);
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bus_space_write_4(s3c2xx0_softc->sc_iot, s3c2xx0_softc->sc_gpio_ioh,
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GPIO_EXTINT(regidx), reg);
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restore_interrupts(save);
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}
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