229 lines
10 KiB
C
229 lines
10 KiB
C
/* $NetBSD: omap5912_intr.c,v 1.2 2008/11/21 17:13:07 matt Exp $ */
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/*
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* IRQ data specific to the Texas Instruments OMAP5912 processor.
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*/
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/*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain this list of conditions
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* and the following disclaimer.
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* 2. Redistributions in binary form must reproduce this list of conditions
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* and the following disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
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* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
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* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ANY
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: omap5912_intr.c,v 1.2 2008/11/21 17:13:07 matt Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/malloc.h>
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <machine/lock.h>
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#include <arm/omap/omap_reg.h>
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#include <arm/omap/omap_tipb.h>
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/*
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* INTC autoconf glue
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*/
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CFATTACH_DECL_NEW(omap5912intc, 0,
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omapintc_match, omapintc_attach, NULL, NULL);
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#define IRQ_TO_BANK_BASE(irq) \
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(((irq) < OMAP_INT_L1_NIRQ) \
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? OMAP_INT_L1_BASE \
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: OMAP_INT_L2_BASE \
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+ (irq-OMAP_INT_L1_NIRQ)/OMAP_BANK_WIDTH*OMAP_INTL2_BANK_OFF)
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#define IRQ_TO_BANK_NUM(irq) \
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((irq)/OMAP_BANK_WIDTH)
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#define IRQ_TO_ILR(irq) \
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(IRQ_TO_BANK_BASE(irq) + \
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OMAP_INTB_ILR_BASE + \
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(irq) % OMAP_BANK_WIDTH * 4)
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#define IRQ_TO_MASK(irq) \
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(1 << (irq) % OMAP_BANK_WIDTH)
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#define INTR_INFO(irq,t) \
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[irq] = { \
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.trig = (t), \
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.bank_base = IRQ_TO_BANK_BASE(irq), \
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.bank_num = IRQ_TO_BANK_NUM(irq), \
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.ILR = IRQ_TO_ILR(irq), \
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.mask = IRQ_TO_MASK(irq) \
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}
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const omap_intr_info_t omap_intr_info[OMAP_NIRQ] = {
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INTR_INFO( 0, TRIG_LEVEL), /* Level 2 IRQ */
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INTR_INFO( 1, TRIG_LEVEL), /* Camera IF */
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INTR_INFO( 2, TRIG_LEVEL), /* Level 2 FIQ */
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INTR_INFO( 3, TRIG_LEVEL_OR_EDGE), /* External FIQ */
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INTR_INFO( 4, TRIG_EDGE), /* McBSP2 TX */
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INTR_INFO( 5, TRIG_EDGE), /* McBSP2 RX */
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INTR_INFO( 6, TRIG_EDGE), /* IRQ_RTDX */
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INTR_INFO( 7, TRIG_LEVEL), /* IRQ_DSP_MMU_ABORT */
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INTR_INFO( 8, TRIG_EDGE), /* IRQ_HOST_INT */
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INTR_INFO( 9, TRIG_LEVEL), /* IRQ_ABORT */
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INTR_INFO( 10, TRIG_LEVEL), /* IRQ_DSP_MAILBOX1 */
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INTR_INFO( 11, TRIG_LEVEL), /* IRQ_DSP_MAILBOX2 */
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INTR_INFO( 12, TRIG_LEVEL), /* IRQ_LCD_LINE */
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INTR_INFO( 13, TRIG_LEVEL), /* Private TIPB Abort */
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INTR_INFO( 14, TRIG_LEVEL), /* IRQ1_GPIO1 */
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INTR_INFO( 15, TRIG_LEVEL), /* UART3 */
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INTR_INFO( 16, TRIG_EDGE), /* IRQ_TIMER3 */
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INTR_INFO( 17, TRIG_LEVEL), /* GPTIMER1 */
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INTR_INFO( 18, TRIG_LEVEL), /* GPTIMER2 */
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INTR_INFO( 19, TRIG_LEVEL), /* IRQ_DMA_CH0 */
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INTR_INFO( 20, TRIG_LEVEL), /* IRQ_DMA_CH1 */
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INTR_INFO( 21, TRIG_LEVEL), /* IRQ_DMA_CH2 */
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INTR_INFO( 22, TRIG_LEVEL), /* IRQ_DMA_CH3 */
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INTR_INFO( 23, TRIG_LEVEL), /* IRQ_DMA_CH4 */
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INTR_INFO( 24, TRIG_LEVEL), /* IRQ_DMA_CH5 */
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INTR_INFO( 25, TRIG_LEVEL), /* IRQ_DMA_CH_LCD */
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INTR_INFO( 26, TRIG_EDGE), /* IRQ_TIMER1 */
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INTR_INFO( 27, TRIG_EDGE), /* IRQ_WD_TIMER */
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INTR_INFO( 28, TRIG_LEVEL), /* Public TIPB Abort */
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INTR_INFO( 30, TRIG_EDGE), /* IRQ_TIMER2 */
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INTR_INFO( 31, TRIG_EDGE), /* IRQ_LCD_CTRL */
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INTR_INFO(OMAP_INT_L1_NIRQ+ 0, TRIG_LEVEL), /* FAC */
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INTR_INFO(OMAP_INT_L1_NIRQ+ 1, TRIG_EDGE), /* Keyboard */
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INTR_INFO(OMAP_INT_L1_NIRQ+ 2, TRIG_LEVEL), /* uWIRE TX */
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INTR_INFO(OMAP_INT_L1_NIRQ+ 3, TRIG_LEVEL), /* uWIRE RX */
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INTR_INFO(OMAP_INT_L1_NIRQ+ 4, TRIG_LEVEL), /* I2C */
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INTR_INFO(OMAP_INT_L1_NIRQ+ 5, TRIG_LEVEL), /* MPUIO */
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INTR_INFO(OMAP_INT_L1_NIRQ+ 6, TRIG_LEVEL), /* USB HHC 1 */
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INTR_INFO(OMAP_INT_L1_NIRQ+ 7, TRIG_LEVEL), /* USB HHC 2 */
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INTR_INFO(OMAP_INT_L1_NIRQ+ 8, TRIG_LEVEL), /* USB_OTG */
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INTR_INFO(OMAP_INT_L1_NIRQ+ 10, TRIG_EDGE), /* McBSP3 TX */
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INTR_INFO(OMAP_INT_L1_NIRQ+ 11, TRIG_EDGE), /* McBSP3 RX */
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INTR_INFO(OMAP_INT_L1_NIRQ+ 12, TRIG_EDGE), /* McBSP1 TX */
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INTR_INFO(OMAP_INT_L1_NIRQ+ 13, TRIG_EDGE), /* McBSP1 RX */
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INTR_INFO(OMAP_INT_L1_NIRQ+ 14, TRIG_LEVEL), /* UART1 */
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INTR_INFO(OMAP_INT_L1_NIRQ+ 15, TRIG_LEVEL), /* UART2 */
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INTR_INFO(OMAP_INT_L1_NIRQ+ 16, TRIG_LEVEL), /* MCSI1 */
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INTR_INFO(OMAP_INT_L1_NIRQ+ 17, TRIG_LEVEL), /* MCSI2 */
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INTR_INFO(OMAP_INT_L1_NIRQ+ 18, TRIG_EDGE), /* Free 1 */
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INTR_INFO(OMAP_INT_L1_NIRQ+ 20, TRIG_LEVEL), /* USB Geni IT */
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INTR_INFO(OMAP_INT_L1_NIRQ+ 21, TRIG_LEVEL), /* 1-Wire */
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INTR_INFO(OMAP_INT_L1_NIRQ+ 22, TRIG_EDGE), /* OS timer */
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INTR_INFO(OMAP_INT_L1_NIRQ+ 23, TRIG_LEVEL), /* MMC/SDIO1 */
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INTR_INFO(OMAP_INT_L1_NIRQ+ 24, TRIG_EDGE), /* USB client wakeup */
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INTR_INFO(OMAP_INT_L1_NIRQ+ 25, TRIG_EDGE), /* RTC periodic */
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INTR_INFO(OMAP_INT_L1_NIRQ+ 26, TRIG_LEVEL), /* RTC alarm */
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INTR_INFO(OMAP_INT_L1_NIRQ+ 28, TRIG_LEVEL), /* DSP_MMU_IRQ */
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INTR_INFO(OMAP_INT_L1_NIRQ+ 29, TRIG_LEVEL), /* USB IRQ_ISO_ON */
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INTR_INFO(OMAP_INT_L1_NIRQ+ 30, TRIG_LEVEL), /* USB IRQ_NON_ISO_ON */
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INTR_INFO(OMAP_INT_L1_NIRQ+ 34, TRIG_LEVEL), /* GPTIMER3 */
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INTR_INFO(OMAP_INT_L1_NIRQ+ 35, TRIG_LEVEL), /* GPTIMER4 */
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INTR_INFO(OMAP_INT_L1_NIRQ+ 36, TRIG_LEVEL), /* GPTIMER5 */
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INTR_INFO(OMAP_INT_L1_NIRQ+ 37, TRIG_LEVEL), /* GPTIMER6 */
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INTR_INFO(OMAP_INT_L1_NIRQ+ 38, TRIG_LEVEL), /* GPTIMER7 */
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INTR_INFO(OMAP_INT_L1_NIRQ+ 39, TRIG_LEVEL), /* GPTIMER8 */
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INTR_INFO(OMAP_INT_L1_NIRQ+ 40, TRIG_LEVEL), /* IRQ1_GPIO2 */
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INTR_INFO(OMAP_INT_L1_NIRQ+ 41, TRIG_LEVEL), /* IRQ1_GPIO3 */
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INTR_INFO(OMAP_INT_L1_NIRQ+ 42, TRIG_LEVEL), /* MMC/SDIO2 */
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INTR_INFO(OMAP_INT_L1_NIRQ+ 43, TRIG_EDGE), /* CompactFlash */
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INTR_INFO(OMAP_INT_L1_NIRQ+ 44, TRIG_LEVEL), /* COMMRX */
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INTR_INFO(OMAP_INT_L1_NIRQ+ 45, TRIG_LEVEL), /* COMMTX */
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INTR_INFO(OMAP_INT_L1_NIRQ+ 46, TRIG_EDGE), /* Peripheral wake up */
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INTR_INFO(OMAP_INT_L1_NIRQ+ 47, TRIG_EDGE), /* Free 2 */
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INTR_INFO(OMAP_INT_L1_NIRQ+ 48, TRIG_LEVEL), /* IRQ1_GPIO4 */
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INTR_INFO(OMAP_INT_L1_NIRQ+ 49, TRIG_LEVEL), /* SPI */
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INTR_INFO(OMAP_INT_L1_NIRQ+ 53, TRIG_LEVEL), /* IRQ_DMA_CH6 */
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INTR_INFO(OMAP_INT_L1_NIRQ+ 54, TRIG_LEVEL), /* IRQ_DMA_CH7 */
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INTR_INFO(OMAP_INT_L1_NIRQ+ 55, TRIG_LEVEL), /* IRQ_DMA_CH8 */
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INTR_INFO(OMAP_INT_L1_NIRQ+ 56, TRIG_LEVEL), /* IRQ_DMA_CH9 */
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INTR_INFO(OMAP_INT_L1_NIRQ+ 57, TRIG_LEVEL), /* IRQ_DMA_CH10 */
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INTR_INFO(OMAP_INT_L1_NIRQ+ 58, TRIG_LEVEL), /* IRQ_DMA_CH11 */
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INTR_INFO(OMAP_INT_L1_NIRQ+ 59, TRIG_LEVEL), /* IRQ_DMA_CH12 */
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INTR_INFO(OMAP_INT_L1_NIRQ+ 60, TRIG_LEVEL), /* IRQ_DMA_CH13 */
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INTR_INFO(OMAP_INT_L1_NIRQ+ 61, TRIG_LEVEL), /* IRQ_DMA_CH14 */
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INTR_INFO(OMAP_INT_L1_NIRQ+ 62, TRIG_LEVEL), /* IRQ_DMA_CH15 */
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INTR_INFO(OMAP_INT_L1_NIRQ+ 66, TRIG_EDGE), /* Free 3 */
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INTR_INFO(OMAP_INT_L1_NIRQ+ 91, TRIG_LEVEL), /* SHA1/MD5 */
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INTR_INFO(OMAP_INT_L1_NIRQ+ 92, TRIG_LEVEL), /* RNG */
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INTR_INFO(OMAP_INT_L1_NIRQ+ 93, TRIG_LEVEL), /* RNGIDLE */
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INTR_INFO(OMAP_INT_L1_NIRQ+103, TRIG_EDGE), /* Free 4 */
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INTR_INFO(OMAP_INT_L1_NIRQ+104, TRIG_EDGE), /* Free 5 */
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INTR_INFO(OMAP_INT_L1_NIRQ+105, TRIG_EDGE), /* Free 6 */
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INTR_INFO(OMAP_INT_L1_NIRQ+106, TRIG_EDGE), /* Free 7 */
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INTR_INFO(OMAP_INT_L1_NIRQ+107, TRIG_EDGE), /* Free 8 */
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INTR_INFO(OMAP_INT_L1_NIRQ+108, TRIG_EDGE), /* Free 9 */
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INTR_INFO(OMAP_INT_L1_NIRQ+109, TRIG_EDGE), /* Free 10 */
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INTR_INFO(OMAP_INT_L1_NIRQ+110, TRIG_EDGE), /* Free 11 */
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INTR_INFO(OMAP_INT_L1_NIRQ+111, TRIG_EDGE), /* Free 12 */
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INTR_INFO(OMAP_INT_L1_NIRQ+112, TRIG_EDGE), /* Free 13 */
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INTR_INFO(OMAP_INT_L1_NIRQ+113, TRIG_EDGE), /* Free 14 */
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INTR_INFO(OMAP_INT_L1_NIRQ+114, TRIG_EDGE), /* Free 15 */
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INTR_INFO(OMAP_INT_L1_NIRQ+115, TRIG_EDGE), /* Free 16 */
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INTR_INFO(OMAP_INT_L1_NIRQ+116, TRIG_EDGE), /* Free 17 */
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INTR_INFO(OMAP_INT_L1_NIRQ+117, TRIG_EDGE), /* Free 18 */
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INTR_INFO(OMAP_INT_L1_NIRQ+118, TRIG_EDGE), /* Free 19 */
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INTR_INFO(OMAP_INT_L1_NIRQ+119, TRIG_EDGE), /* Free 20 */
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INTR_INFO(OMAP_INT_L1_NIRQ+120, TRIG_EDGE), /* Free 21 */
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INTR_INFO(OMAP_INT_L1_NIRQ+121, TRIG_EDGE), /* Free 22 */
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INTR_INFO(OMAP_INT_L1_NIRQ+122, TRIG_EDGE), /* Free 23 */
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INTR_INFO(OMAP_INT_L1_NIRQ+123, TRIG_EDGE), /* Free 24 */
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INTR_INFO(OMAP_INT_L1_NIRQ+124, TRIG_EDGE), /* Free 25 */
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INTR_INFO(OMAP_INT_L1_NIRQ+125, TRIG_EDGE), /* Free 26 */
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INTR_INFO(OMAP_INT_L1_NIRQ+126, TRIG_EDGE), /* Free 27 */
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INTR_INFO(OMAP_INT_L1_NIRQ+127, TRIG_EDGE), /* Free 28 */
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};
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/* Array of pointers to each bank's base. */
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vaddr_t omap_intr_bank_bases[OMAP_NBANKS] = {
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OMAP_INT_L1_BASE,
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OMAP_INT_L2_BASE + 0*OMAP_INTL2_BANK_OFF,
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OMAP_INT_L2_BASE + 1*OMAP_INTL2_BANK_OFF,
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OMAP_INT_L2_BASE + 2*OMAP_INTL2_BANK_OFF,
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OMAP_INT_L2_BASE + 3*OMAP_INTL2_BANK_OFF,
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};
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/* Array to translate from software interrupt numbers to an irq number. */
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int omap_si_to_irq[OMAP_FREE_IRQ_NUM] = {
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OMAP_INT_L1_NIRQ+ 18, /* Free 1 */
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OMAP_INT_L1_NIRQ+ 47, /* Free 2 */
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OMAP_INT_L1_NIRQ+ 66, /* Free 3 */
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OMAP_INT_L1_NIRQ+103, /* Free 4 */
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OMAP_INT_L1_NIRQ+104, /* Free 5 */
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OMAP_INT_L1_NIRQ+105, /* Free 6 */
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OMAP_INT_L1_NIRQ+106, /* Free 7 */
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OMAP_INT_L1_NIRQ+107, /* Free 8 */
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OMAP_INT_L1_NIRQ+108, /* Free 9 */
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OMAP_INT_L1_NIRQ+109, /* Free 10 */
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OMAP_INT_L1_NIRQ+110, /* Free 11 */
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OMAP_INT_L1_NIRQ+111, /* Free 12 */
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OMAP_INT_L1_NIRQ+112, /* Free 13 */
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OMAP_INT_L1_NIRQ+113, /* Free 14 */
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OMAP_INT_L1_NIRQ+114, /* Free 15 */
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OMAP_INT_L1_NIRQ+115, /* Free 16 */
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OMAP_INT_L1_NIRQ+116, /* Free 17 */
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OMAP_INT_L1_NIRQ+117, /* Free 18 */
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OMAP_INT_L1_NIRQ+118, /* Free 19 */
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OMAP_INT_L1_NIRQ+119, /* Free 20 */
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OMAP_INT_L1_NIRQ+120, /* Free 21 */
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OMAP_INT_L1_NIRQ+121, /* Free 22 */
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OMAP_INT_L1_NIRQ+122, /* Free 23 */
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OMAP_INT_L1_NIRQ+123, /* Free 24 */
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OMAP_INT_L1_NIRQ+124, /* Free 25 */
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OMAP_INT_L1_NIRQ+125, /* Free 26 */
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OMAP_INT_L1_NIRQ+126, /* Free 27 */
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OMAP_INT_L1_NIRQ+127, /* Free 28 */
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};
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