340 lines
9.2 KiB
C
340 lines
9.2 KiB
C
/* $NetBSD: omap2_mputmr.c,v 1.1 2008/08/27 11:03:10 matt Exp $ */
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/*
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* OMAP 2430 GP timers
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*/
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/*
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* Based on i80321_timer.c and arch/arm/sa11x0/sa11x0_ost.c
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*
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* Copyright (c) 1997 Mark Brinicombe.
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* Copyright (c) 1997 Causality Limited.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by IWAMOTO Toshihiro and Ichiro FUKUHARA.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* Copyright (c) 2001, 2002 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Jason R. Thorpe for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: omap2_mputmr.c,v 1.1 2008/08/27 11:03:10 matt Exp $");
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#include "opt_omap.h"
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#include "opt_cpuoptions.h"
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#include <sys/types.h>
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/time.h>
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#include <sys/timetc.h>
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#include <sys/device.h>
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#include <dev/clock_subr.h>
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <arm/omap/omap_gptmrreg.h>
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#include <arm/omap/omap2_mputmrvar.h>
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#ifndef ARM11_PMC
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uint32_t counts_per_usec, counts_per_hz;
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#endif
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struct mputmr_softc *clock_sc;
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struct mputmr_softc *stat_sc;
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struct mputmr_softc *ref_sc;
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static uint32_t mpu_get_timecount(struct timecounter *);
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static struct timecounter mpu_timecounter = {
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.tc_get_timecount = mpu_get_timecount,
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.tc_counter_mask = 0xffffffff,
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.tc_frequency = OMAP_MPU_TIMER_CLOCK_FREQ,
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.tc_name = "gpt",
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.tc_quality = 100,
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.tc_priv = NULL
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};
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static inline void
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_timer_intr_dis(struct mputmr_softc *sc)
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{
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bus_space_write_4(sc->sc_iot, sc->sc_ioh, TIER, 0);
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}
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static inline void
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_timer_intr_enb(struct mputmr_softc *sc)
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{
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bus_space_write_4(sc->sc_iot, sc->sc_ioh, TIER, TIER_OVF_IT_ENA);
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}
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static inline uint32_t
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_timer_intr_sts(struct mputmr_softc *sc)
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{
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return bus_space_read_4(sc->sc_iot, sc->sc_ioh, TISR);
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}
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static inline void
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_timer_intr_ack(struct mputmr_softc *sc)
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{
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bus_space_write_4(sc->sc_iot, sc->sc_ioh, TISR, TIER_OVF_IT_ENA);
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}
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static inline uint32_t
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_timer_read(struct mputmr_softc *sc)
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{
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return bus_space_read_4(sc->sc_iot, sc->sc_ioh, TCRR);
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}
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static inline void
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_timer_stop(struct mputmr_softc *sc)
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{
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uint32_t r;
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r = bus_space_read_4(sc->sc_iot, sc->sc_ioh, TCLR);
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r &= ~TCLR_ST;
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bus_space_write_4(sc->sc_iot, sc->sc_ioh, TCLR, r);
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}
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static inline void
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_timer_reload(struct mputmr_softc *sc, uint32_t val)
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{
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bus_space_write_4(sc->sc_iot, sc->sc_ioh, TLDR, val);
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bus_space_write_4(sc->sc_iot, sc->sc_ioh, TCRR, val);
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}
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static inline void
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_timer_start(struct mputmr_softc *sc, timer_factors *tfp)
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{
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uint32_t r=0;
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if (tfp->ptv != 0) {
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r |= TCLR_PRE(1);
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r |= (TCLR_PTV(tfp->ptv - 1) & TCLR_PTV_MASK);
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}
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r |= (TCLR_CE | TCLR_AR | TCLR_ST);
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bus_space_write_4(sc->sc_iot, sc->sc_ioh, TCLR, r);
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}
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static uint32_t
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mpu_get_timecount(struct timecounter *tc)
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{
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return _timer_read(ref_sc);
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}
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int
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clockintr(void *frame)
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{
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_timer_intr_ack(clock_sc);
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hardclock(frame);
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return 1;
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}
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int
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statintr(void *frame)
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{
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_timer_intr_ack(stat_sc);
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statclock(frame);
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return 1;
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}
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static void
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setclockrate(struct mputmr_softc *sc, int schz)
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{
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timer_factors tf;
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_timer_stop(sc);
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calc_timer_factors(schz, &tf);
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_timer_reload(sc, tf.reload);
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_timer_start(sc, &tf);
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}
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void
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setstatclockrate(int schz)
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{
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setclockrate(stat_sc, schz);
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}
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void
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cpu_initclocks(void)
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{
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if (clock_sc == NULL)
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panic("Clock timer was not configured.");
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if (stat_sc == NULL)
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panic("Statistics timer was not configured.");
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if (ref_sc == NULL)
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panic("Microtime reference timer was not configured.");
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/*
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* We already have the timers running, but not generating interrupts.
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* In addition, we've set stathz and profhz.
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*/
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printf("clock: hz=%d stathz=%d\n", hz, stathz);
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_timer_intr_dis(clock_sc);
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_timer_intr_dis(stat_sc);
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_timer_intr_dis(ref_sc);
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setclockrate(clock_sc, hz);
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setclockrate(stat_sc, stathz);
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setclockrate(ref_sc, 0);
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/*
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* The "cookie" parameter must be zero to pass the interrupt frame
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* through to hardclock() and statclock().
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*/
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intr_establish(clock_sc->sc_intr, IPL_CLOCK, IST_LEVEL, clockintr, 0);
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intr_establish(stat_sc->sc_intr, IPL_HIGH, IST_LEVEL, statintr, 0);
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_timer_intr_enb(clock_sc);
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_timer_intr_enb(stat_sc);
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tc_init(&mpu_timecounter);
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}
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#ifndef ARM11_PMC
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void
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delay(u_int n)
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{
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uint32_t cur, last, delta, usecs;
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if (clock_sc == NULL)
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panic("The timer must be initialized sooner.");
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/*
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* This works by polling the timer and counting the
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* number of microseconds that go by.
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*/
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last = _timer_read(clock_sc);
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delta = usecs = 0;
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while (n > usecs) {
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cur = _timer_read(clock_sc);
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/* Check to see if the timer has wrapped around. */
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if (last < cur)
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delta += (last + (counts_per_hz - cur));
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else
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delta += (last - cur);
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last = cur;
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if (delta >= counts_per_usec) {
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usecs += delta / counts_per_usec;
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delta %= counts_per_usec;
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}
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}
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}
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#endif /* ARM11_PMC */
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/*
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* OVF_Rate =
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* (0xFFFFFFFF - GPTn.TLDR + 1) * (timer functional clock period) * PS
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*/
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void
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calc_timer_factors(int ints_per_sec, timer_factors *tf)
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{
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uint32_t ptv_power; /* PS */
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uint32_t count_freq;
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const uint32_t us_per_sec = 1000000;
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if (ints_per_sec == 0) {
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/*
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* When ints_per_sec equal to zero there is mean full range
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* timer usage. Nevertheless autoreload mode is still enabled.
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*/
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tf->ptv = 0;
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tf->reload = 0;
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tf->counts_per_usec = OMAP_MPU_TIMER_CLOCK_FREQ / us_per_sec;
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return;
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}
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tf->ptv = 8;
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for (;;) {
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ptv_power = 1 << tf->ptv;
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count_freq = OMAP_MPU_TIMER_CLOCK_FREQ;
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count_freq /= hz;
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count_freq /= ptv_power;
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tf->reload = -count_freq;
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tf->counts_per_usec = count_freq / us_per_sec;
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if ((tf->reload * ptv_power * ints_per_sec
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== OMAP_MPU_TIMER_CLOCK_FREQ)
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&& (tf->counts_per_usec * ptv_power * us_per_sec
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== OMAP_MPU_TIMER_CLOCK_FREQ))
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{ /* Exact match. Life is good. */
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/* Currently reload is MPU_LOAD_TIMER+1. Fix it. */
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tf->reload--;
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return;
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}
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if (tf->ptv == 0) {
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tf->counts_per_usec++;
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return;
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}
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tf->ptv--;
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}
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}
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