131 lines
5.1 KiB
Plaintext
131 lines
5.1 KiB
Plaintext
# $NetBSD: files.omap,v 1.5 2007/12/03 15:33:19 ad Exp $
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#
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# Configuration info for Texas Instruments OMAP CPU support
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# Based on xscale/files.pxa2x0
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#
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file arch/arm/arm32/irq_dispatch.S
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# Memory size in megabytes
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defparam opt_omap.h MEMSIZE
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# Texas Instruments Peripheral Bus.
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# addr: Address of the peripheral in the OMAP address space
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# size: Number of bytes that the peripheral occupies in the OMAP address space
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# intr: Interrupts connected to the first level interrupt controller should
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# give the first level interrupt controller's number. Interrupts
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# connected to the second level interrupt controller should give the
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# second level interrupt controller's number plus 32 (the number of
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# interrupts that the first level controller has).
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# mult: Used to multiply the offsets given within a driver. For example, if
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# the driver expects byte registers at byte offsets, but they are mapped
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# in at word offsets, a mult of 4 would be specified. Note that the
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# size parameter is not multiplied by mult. If you specify a mult, in
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# general, you should probably be specifying a size to ensure that the
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# correct amount is mapped.
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device tipb { [addr=-1], [size=0], [intr=-1], [mult=1] } : bus_space_generic
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attach tipb at mainbus
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file arch/arm/omap/omap_tipb.c tipb
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defparam opt_omap.h OMAP_TIPB_PBASE OMAP_TIPB_SIZE
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# Extended Memory Interface Slow
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# Same parameters as for TIPB, but with the addition of parameters to
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# configure bus access. A parameter is provided to to force halfword access
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# instead of byte accesses:
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# nobyteacc: Allow 8-bit access for device with no lsb address line
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# If this is set to 1, if an attempt is made to write a single byte to the
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# bus, it will automatically get converted into reading a halfword, setting
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# the byte that is being written into the appropriate byte of the halfword,
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# and then writing the halfword to the bus.
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#
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# In addition to the nobyteacc parameter, a number of parameters are provided
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# to configure bus timing via the EMIFS_CCS and EMIFS_ACS registers. The cs
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# parameter specifies which chip-select should have its configuration
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# modified.
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#
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# NOTE: If the cs parameter is not specified, the EMIFS_CCS and EMIFS_ACS
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# registers will not be modified and all of the bus timing parameters will be
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# ignored.
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#
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# When cs is specified, EMIFS_CCS and EMIFS_ACS will be modified. In addition
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# to cs on your emifs device, you must specify the base parameter on the emifs
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# bus to tell it where its registers are. All fields of the EMIFS_CCS and
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# EMIFS_ACS registers will be set. The EMIFS will be set to be:
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#
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# asynchronous, non-page mode (RDMODE = 0)
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# non-multiplexed protocol
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# 16 bit wide
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# REF_CLK = TC_CK / 1
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#
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# The timing parameters are rdwst, oesetup, oehold, wrwst, welen, advhold,
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# btwst and btmode. All of them specify a number of nanoseconds, except
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# btmode which is a simple 0/1 flag.
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#
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# For a read cycle, CS will be held low for rdwst nanoseconds. The delay from
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# driving CS low to driving OE low is specified by oesetup. OE will go back
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# high oehold nanoseconds before CS goes back high.
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#
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# For a write cycle, CS will be held low for wrwst (time before WE goes low) +
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# welen (time WE is held low) + 1 REF_CLK cycle (time after WE goes high).
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#
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# For both read and write, advhold specifies how long ADV should be remain low
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# after it is driven low at the same time as CS.
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#
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# The bus turn around time (amount of time that CS needs to be high between
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# accesses) is specified by btwst and btmode. See the TRM for more
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# information.
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#
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# If btmode is not specified, it will be set to 0. All other timing
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# parameters will default to their minimum value.
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#
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device emifs { [addr=-1], [size=0], [intr=-1], [mult=1], [nobyteacc=0],
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[cs=-1], [rdwst=0], [oesetup=0], [oehold=0],
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[wrwst=0], [welen=0], [advhold=0], [btwst=0], [btmode=0]
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} : bus_space_generic
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attach emifs at mainbus
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file arch/arm/omap/omap_emifs.c emifs
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file arch/arm/omap/omap_nobyteacc_space.c emifs
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file arch/arm/omap/omap_nobyteacc_io.S emifs
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defparam opt_omap.h OMAP_TC_CLOCK_FREQ
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# OCP
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device ocp { [addr=-1], [size=0], [intr=-1], [mult=1]} : bus_space_generic
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attach ocp at mainbus
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file arch/arm/omap/omap_ocp.c ocp
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# TIPB/EMIFS/OCP common files
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file arch/arm/omap/omap_space.c tipb | emifs | ocp
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file arch/arm/omap/omap_a2x_space.c tipb | emifs | ocp
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file arch/arm/omap/omap_a2x_io.S tipb | emifs | ocp
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file arch/arm/omap/omap_a4x_space.c tipb | emifs | ocp
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file arch/arm/xscale/pxa2x0_a4x_io.S tipb | emifs | ocp
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# NS16550 compatible serial ports
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attach com at tipb with omapuart
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file arch/arm/omap/omap_com.c omapuart
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defparam opt_com.h CONSADDR CONSPEED CONMODE
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# INTC controller
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define omapintc
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file arch/arm/omap/omap_intr.c omapintc
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# OMAP5912 specific INTC controller code
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device omap5912intc: omapintc
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attach omap5912intc at tipb
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file arch/arm/omap/omap5912_intr.c omap5912intc
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# MPU Timer
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device omapmputmr
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attach omapmputmr at tipb
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file arch/arm/omap/omap_mputmr.c omapmputmr
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defparam opt_omap.h OMAP_MPU_TIMER_CLOCK_FREQ
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# OMAP GPIO Block
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device omapgpio
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attach omapgpio at tipb
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file arch/arm/omap/omap_gpio.c omapgpio needs-count
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# RTC
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device omaprtc
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attach omaprtc at tipb
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file arch/arm/omap/omap_rtc.c omaprtc
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