81 lines
3.4 KiB
C
81 lines
3.4 KiB
C
/* $Id: at91streg.h,v 1.2 2008/07/03 01:15:38 matt Exp $ */
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/* $NetBSD: at91streg.h,v 1.2 2008/07/03 01:15:38 matt Exp $ */
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/*-
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* Copyright (c) 2007 Embedtronics Oy
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#ifndef _AT91STREG_H_
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#define _AT91STREG_H_
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#define AT91ST_BASE 0xFFFFFD00UL
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/* System Timer (ST),
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* at91rm9200.pdf, page 289: */
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#define ST_CR 0x00UL /* 0x00: Control Register (W/O) */
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#define ST_PIMR 0x04UL /* 0x04: Period Interval Mode Reg */
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#define ST_WDMR 0x08UL /* 0x08: Watchdog Mode Reg */
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#define ST_RTMR 0x0CUL /* 0x0C: Real-time Mode Reg */
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#define ST_SR 0x10UL /* 0x10: Status Register */
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#define ST_IER 0x14UL /* 0x14: Interrupt Enable Register */
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#define ST_IDR 0x18UL /* 0x18: Interrupt Disable Register */
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#define ST_IMR 0x1CUL /* 0x1C: Interrupt Mask Register */
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#define ST_RTAR 0x20UL /* 0x20: Real-time Alarm Register */
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#define ST_CRTR 0x24UL /* 0x24: Current Real-time Register */
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/* Control Register bits: */
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#define ST_CR_WDRST 0x1 /* 1=reload the start-up value in wdt */
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/* Watchdog Mode Register bits: */
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#define ST_WDMR_EXTEN 0x20000 /* 1 = external signal assertion enable */
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#define ST_WDMR_RSTEN 0x10000 /* 1 = generate internal reset on wdt */
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#define ST_WDMR_WDV 0xFFFF
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/* Status Register bits: */
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#define ST_SR_ALMS 0x8 /* 1 = alarm compare detected */
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#define ST_SR_RTTINC 0x4 /* 1 = real-time timer incremented */
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#define ST_SR_WDOVF 0x2 /* 1 = watchdog overflowed */
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#define ST_SR_PITS 0x1 /* 1 = period interval timer overflowed */
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/* CRTR */
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#define ST_CRTR_CRTV 0xFFFFF
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#define ST_CRTR_CRTV_BITS 20
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/* watchdog macros */
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#define WDT_TIMEOUT 20000 /* milliseconds */
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//
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#define STREG(reg) *((volatile u_int32_t *)(AT91ST_BASE + (reg)))
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#define WDog() do {CPUReg->ST.CR = ST_CR_WDRST;} while (0)
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#endif /* _AT91STREG_H_ */
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