472 lines
11 KiB
C
472 lines
11 KiB
C
/* $Id: at91aic.c,v 1.2 2008/07/03 01:15:38 matt Exp $ */
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/* $NetBSD: at91aic.c,v 1.2 2008/07/03 01:15:38 matt Exp $ */
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/*
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* Copyright (c) 2007 Embedtronics Oy.
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* All rights reserved.
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*
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* Based on ep93xx_intr.c
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* Copyright (c) 2002 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jesse Off
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Ichiro FUKUHARA and Naoto Shimazaki.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Interrupt support for the Atmel's AT91xx9xxx family controllers
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/malloc.h>
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#include <sys/termios.h>
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#include <uvm/uvm_extern.h>
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <arm/cpufunc.h>
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#include <arm/at91/at91reg.h>
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#include <arm/at91/at91var.h>
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#include <arm/at91/at91aicreg.h>
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#include <arm/at91/at91aicvar.h>
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#define NIRQ 32
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/* Interrupt handler queues. */
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struct intrq intrq[NIRQ];
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/* Interrupts to mask at each level. */
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static u_int32_t aic_imask[NIPL];
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/* Software copy of the IRQs we have enabled. */
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volatile u_int32_t aic_intr_enabled;
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#define AICREG(reg) *((volatile u_int32_t*) (AT91AIC_BASE + (reg)))
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static int at91aic_match(device_t, cfdata_t, void *);
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static void at91aic_attach(device_t, device_t, void *);
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CFATTACH_DECL(at91aic, sizeof(struct device),
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at91aic_match, at91aic_attach, NULL, NULL);
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static int
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at91aic_match(device_t parent, cfdata_t match, void *aux)
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{
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if (strcmp(match->cf_name, "at91aic") == 0)
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return 2;
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return 0;
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}
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static void
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at91aic_attach(device_t parent, device_t self, void *aux)
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{
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(void)parent; (void)self; (void)aux;
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printf("\n");
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}
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static inline void
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at91_set_intrmask(u_int32_t aic_irqs)
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{
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AICREG(AIC_IDCR) = aic_irqs;
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AICREG(AIC_IECR) = aic_intr_enabled & ~aic_irqs;
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}
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static inline void
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at91_enable_irq(int irq)
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{
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aic_intr_enabled |= (1U << irq);
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AICREG(AIC_IECR) = (1U << irq);
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}
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static inline void
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at91_disable_irq(int irq)
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{
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aic_intr_enabled &= ~(1U << irq);
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AICREG(AIC_IDCR) = (1U << irq);
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}
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/*
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* NOTE: This routine must be called with interrupts disabled in the CPSR.
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*/
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static void
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at91aic_calculate_masks(void)
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{
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struct intrq *iq;
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struct intrhand *ih;
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int irq, ipl;
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/* First, figure out which IPLs each IRQ has. */
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for (irq = 0; irq < NIRQ; irq++) {
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int levels = 0;
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iq = &intrq[irq];
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at91_disable_irq(irq);
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for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL;
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ih = TAILQ_NEXT(ih, ih_list))
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levels |= (1U << ih->ih_ipl);
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iq->iq_levels = levels;
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}
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/* Next, figure out which IRQs are used by each IPL. */
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for (ipl = 0; ipl < NIPL; ipl++) {
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int aic_irqs = 0;
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for (irq = 0; irq < AIC_NIRQ; irq++) {
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if (intrq[irq].iq_levels & (1U << ipl))
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aic_irqs |= (1U << irq);
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}
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aic_imask[ipl] = aic_irqs;
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}
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aic_imask[IPL_NONE] = 0;
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/*
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* splvm() blocks all interrupts that use the kernel memory
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* allocation facilities.
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*/
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aic_imask[IPL_VM] |= aic_imask[IPL_NONE];
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/*
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* splclock() must block anything that uses the scheduler.
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*/
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aic_imask[IPL_CLOCK] |= aic_imask[IPL_VM];
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/*
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* splhigh() must block "everything".
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*/
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aic_imask[IPL_HIGH] |= aic_imask[IPL_CLOCK];
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/*
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* Now compute which IRQs must be blocked when servicing any
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* given IRQ.
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*/
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for (irq = 0; irq < MIN(NIRQ, AIC_NIRQ); irq++) {
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iq = &intrq[irq];
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if (TAILQ_FIRST(&iq->iq_list) != NULL)
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at91_enable_irq(irq);
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}
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/*
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* update current mask
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*/
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at91_set_intrmask(aic_imask[curcpl()]);
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}
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inline void
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splx(int new)
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{
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int old;
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u_int oldirqstate;
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oldirqstate = disable_interrupts(I32_bit);
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old = curcpl();
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if (old != new) {
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set_curcpl(new);
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at91_set_intrmask(aic_imask[new]);
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}
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restore_interrupts(oldirqstate);
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#ifdef __HAVE_FAST_SOFTINTS
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cpu_dosoftints();
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#endif
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}
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int
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_splraise(int ipl)
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{
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int old;
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u_int oldirqstate;
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oldirqstate = disable_interrupts(I32_bit);
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old = curcpl();
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if (old != ipl) {
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set_curcpl(ipl);
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at91_set_intrmask(aic_imask[ipl]);
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}
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restore_interrupts(oldirqstate);
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return (old);
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}
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int
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_spllower(int ipl)
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{
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int old = curcpl();
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if (old <= ipl)
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return (old);
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splx(ipl);
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#ifdef __HAVE_FAST_SOFTINTS
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cpu_dosoftints();
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#endif
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return (old);
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}
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/*
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* at91aic_init:
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*
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* Initialize the rest of the interrupt subsystem, making it
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* ready to handle interrupts from devices.
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*/
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void
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at91aic_init(void)
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{
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struct intrq *iq;
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int i;
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aic_intr_enabled = 0;
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// disable intrrupts:
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AICREG(AIC_IDCR) = -1;
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for (i = 0; i < NIRQ; i++) {
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iq = &intrq[i];
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TAILQ_INIT(&iq->iq_list);
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sprintf(iq->iq_name, "irq %d", i);
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evcnt_attach_dynamic(&iq->iq_ev, EVCNT_TYPE_INTR,
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NULL, "aic", iq->iq_name);
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}
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/* All interrupts should use IRQ not FIQ */
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AICREG(AIC_IDCR) = -1; /* disable interrupts */
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AICREG(AIC_ICCR) = -1; /* clear all interrupts */
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AICREG(AIC_DCR) = 0; /* not in debug mode, just to make sure */
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for (i = 0; i < NIRQ; i++) {
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AICREG(AIC_SMR(i)) = 0; /* disable interrupt */
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AICREG(AIC_SVR(i)) = (u_int32_t)&intrq[i]; // address of interrupt queue
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}
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AICREG(AIC_FVR) = 0; // fast interrupt...
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AICREG(AIC_SPU) = 0; // spurious interrupt vector
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AICREG(AIC_EOICR) = 0; /* clear logic... */
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AICREG(AIC_EOICR) = 0; /* clear logic... */
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at91aic_calculate_masks();
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/* Enable IRQs (don't yet use FIQs). */
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enable_interrupts(I32_bit);
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}
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void *
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at91aic_intr_establish(int irq, int ipl, int type, int (*ih_func)(void *), void *arg)
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{
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struct intrq* iq;
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struct intrhand* ih;
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u_int oldirqstate;
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unsigned ok;
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uint32_t smr;
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if (irq < 0 || irq >= NIRQ)
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panic("intr_establish: IRQ %d out of range", irq);
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if (ipl < 0 || ipl >= NIPL)
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panic("intr_establish: IPL %d out of range", ipl);
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smr = 1; // all interrupts have priority one.. ok?
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switch (type) {
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case _INTR_LOW_LEVEL:
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smr |= AIC_SMR_SRCTYPE_LVL_LO;
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break;
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case INTR_HIGH_LEVEL:
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smr |= AIC_SMR_SRCTYPE_LVL_HI;
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break;
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case INTR_FALLING_EDGE:
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smr |= AIC_SMR_SRCTYPE_FALLING;
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break;
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case INTR_RISING_EDGE:
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smr |= AIC_SMR_SRCTYPE_RISING;
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break;
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default:
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panic("intr_establish: interrupt type %d is invalid", type);
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}
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ih = malloc(sizeof(*ih), M_DEVBUF, M_NOWAIT);
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if (ih == NULL)
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return (NULL);
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ih->ih_func = ih_func;
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ih->ih_arg = arg;
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ih->ih_irq = irq;
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ih->ih_ipl = ipl;
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iq = &intrq[irq];
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oldirqstate = disable_interrupts(I32_bit);
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if (TAILQ_FIRST(&iq->iq_list) == NULL || (iq->iq_type & ~type) == 0) {
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AICREG(AIC_SMR(irq)) = smr;
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iq->iq_type = type;
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TAILQ_INSERT_TAIL(&iq->iq_list, ih, ih_list);
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at91aic_calculate_masks();
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ok = 1;
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} else
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ok = 0;
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restore_interrupts(oldirqstate);
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if (ok) {
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#ifdef AT91AIC_DEBUG
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int i;
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printf("\n");
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for (i = 0; i < NIPL; i++) {
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printf("IPL%d: aic_imask=0x%08X\n", i, aic_imask[i]);
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}
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#endif
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} else {
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free(ih, M_DEVBUF);
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ih = NULL;
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}
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return (ih);
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}
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void
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at91aic_intr_disestablish(void *cookie)
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{
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struct intrhand* ih = cookie;
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struct intrq* iq = &intrq[ih->ih_irq];
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u_int oldirqstate;
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oldirqstate = disable_interrupts(I32_bit);
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TAILQ_REMOVE(&iq->iq_list, ih, ih_list);
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at91aic_calculate_masks();
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restore_interrupts(oldirqstate);
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}
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#include <arm/at91/at91reg.h>
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#include <arm/at91/at91dbgureg.h>
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#include <arm/at91/at91pdcreg.h>
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static inline void intr_process(struct intrq *iq, int pcpl, struct irqframe *frame);
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static inline void
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intr_process(struct intrq *iq, int pcpl, struct irqframe *frame)
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{
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struct intrhand* ih;
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u_int oldirqstate, intr;
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intr = iq - intrq;
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iq->iq_ev.ev_count++;
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uvmexp.intrs++;
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if ((1U << intr) & aic_imask[pcpl]) {
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panic("interrupt %d should be masked! (aic_imask=0x%X)", intr, aic_imask[pcpl]);
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}
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if (iq->iq_busy) {
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panic("interrupt %d busy!", intr);
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}
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iq->iq_busy = 1;
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for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL;
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ih = TAILQ_NEXT(ih, ih_list)) {
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set_curcpl(ih->ih_ipl);
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at91_set_intrmask(aic_imask[ih->ih_ipl]);
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oldirqstate = enable_interrupts(I32_bit);
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(void) (*ih->ih_func)(ih->ih_arg ? ih->ih_arg : frame);
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restore_interrupts(oldirqstate);
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}
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if (!iq->iq_busy) {
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panic("interrupt %d not busy!", intr);
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}
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iq->iq_busy = 0;
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set_curcpl(pcpl);
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at91_set_intrmask(aic_imask[pcpl]);
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}
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void
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at91aic_intr_dispatch(struct irqframe *frame)
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{
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struct intrq* iq;
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int pcpl = curcpl();
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iq = (struct intrq *)AICREG(AIC_IVR); // get current queue
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// OK, service interrupt
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if (iq)
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intr_process(iq, pcpl, frame);
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AICREG(AIC_EOICR) = 0; // end of interrupt
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}
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#if 0
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void
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at91aic_intr_poll(int irq)
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{
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u_int oldirqstate;
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uint32_t ipr;
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int pcpl = curcpl();
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oldirqstate = disable_interrupts(I32_bit);
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ipr = AICREG(AIC_IPR);
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if ((ipr & (1U << irq) & ~aic_imask[pcpl]))
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intr_process(&intrq[irq], pcpl, NULL);
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restore_interrupts(oldirqstate);
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#ifdef __HAVE_FAST_SOFTINTS
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cpu_dosoftints();
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#endif
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}
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#endif
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void
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at91aic_intr_poll(void *ihp, int flags)
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{
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struct intrhand* ih = ihp;
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u_int oldirqstate, irq = ih->ih_irq;
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uint32_t ipr;
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int pcpl = curcpl();
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oldirqstate = disable_interrupts(I32_bit);
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ipr = AICREG(AIC_IPR);
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if ((ipr & (1U << irq))
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&& (flags || !(aic_imask[pcpl] & (1U << irq)))) {
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set_curcpl(ih->ih_ipl);
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at91_set_intrmask(aic_imask[ih->ih_ipl]);
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(void)enable_interrupts(I32_bit);
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(void)(*ih->ih_func)(ih->ih_arg ? ih->ih_arg : NULL);
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(void)disable_interrupts(I32_bit);
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set_curcpl(pcpl);
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at91_set_intrmask(aic_imask[pcpl]);
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}
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restore_interrupts(oldirqstate);
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#ifdef __HAVE_FAST_SOFTINTS
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cpu_dosoftints();
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#endif
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}
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