ba922d31d8
interrupt time. This was the cause of the 'mmu fault' panics seen by several people, as the Tx interrupt is at a higher priority that spltty().
139 lines
5.0 KiB
C
139 lines
5.0 KiB
C
/* $NetBSD: clmpccvar.h,v 1.3 1999/08/01 09:35:05 scw Exp $ */
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/*-
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* Copyright (c) 1999 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Steve C. Woodford.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __clmpccvar_h
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#define __clmpccvar_h
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/* Buffer size for character buffer */
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#define CLMPCC_RING_SIZE 512
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/* How many channels per chip */
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#define CLMPCC_NUM_CHANS 4
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/* Reasons for calling the MD code's iack hook function */
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#define CLMPCC_IACK_MODEM 0
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#define CLMPCC_IACK_RX 1
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#define CLMPCC_IACK_TX 2
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struct clmpcc_softc;
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/*
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* Each channel is represented by one of the following structures
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*/
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struct clmpcc_chan {
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struct tty *ch_tty; /* This channel's tty structure */
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struct clmpcc_softc *ch_sc; /* Pointer to chip's softc structure */
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u_char ch_car; /* Channel number (CD2400_REG_CAR) */
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u_char ch_openflags; /* Persistant TIOC flags */
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volatile u_short ch_flags; /* Various channel-specific flags */
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#define CLMPCC_FLG_IS_CONSOLE 0x0001 /* Channel is system console */
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#define CLMPCC_FLG_START_BREAK 0x0002
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#define CLMPCC_FLG_END_BREAK 0x0004
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#define CLMPCC_FLG_FIFO_CLEAR 0x0008
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#define CLMPCC_FLG_UPDATE_PARMS 0x0010
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#define CLMPCC_FLG_NEED_INIT 0x0020
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u_char ch_tx_done;
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u_char ch_control;
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/* New port parameters wait here until written by the Tx ISR */
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u_char ch_tcor;
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u_char ch_tbpr;
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u_char ch_rcor;
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u_char ch_rbpr;
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u_char ch_cor1;
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u_char ch_cor2;
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u_char ch_cor3;
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u_char ch_cor4; /* Current Rx Fifo threshold */
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u_char ch_cor5;
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u_int8_t *ch_ibuf; /* Start of input ring buffer */
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u_int8_t *ch_ibuf_end; /* End of input ring buffer */
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u_int8_t *ch_ibuf_rd; /* Input buffer tail (reader) */
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u_int8_t *ch_ibuf_wr; /* Input buffer head (writer) */
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u_int8_t *ch_obuf_addr; /* Output buffer address */
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u_int ch_obuf_size; /* Output buffer size (in bytes) */
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};
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struct clmpcc_softc {
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struct device sc_dev;
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/*
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* The bus/MD-specific attachment code must initialise the
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* following fields before calling 'clmpcc_attach_subr()'.
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*/
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bus_space_tag_t sc_iot; /* Tag for parent bus */
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bus_space_handle_t sc_ioh; /* Handle for chip's regs */
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void *sc_data; /* MD-specific data */
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int sc_clk; /* Clock-rate, in Hz */
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u_char sc_vector_base; /* Vector base reg, or 0 for auto */
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u_char sc_rpilr; /* Receive Priority Interupt Level */
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u_char sc_tpilr; /* Transmit Priority Interupt Level */
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u_char sc_mpilr; /* Modem Priority Interupt Level */
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int sc_swaprtsdtr; /* Non-zero if RTS and DTR swapped */
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u_int sc_byteswap; /* One of the following ... */
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#define CLMPCC_BYTESWAP_LOW 0x00 /* *byteswap pin is low */
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#define CLMPCC_BYTESWAP_HIGH 0x03 /* *byteswap pin is high */
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/* Called to request a soft interrupt callback to clmpcc_softintr */
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void (*sc_softhook) __P((struct clmpcc_softc *));
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/* Called when an interrupt has to be acknowledged in polled mode. */
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void (*sc_iackhook) __P((struct clmpcc_softc *, int));
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/*
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* No user-serviceable parts below
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*/
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volatile int sc_soft_running;
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struct clmpcc_chan sc_chans[CLMPCC_NUM_CHANS];
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};
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extern void clmpcc_attach __P((struct clmpcc_softc *));
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extern int clmpcc_cnattach __P((struct clmpcc_softc *, int, int));
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extern int clmpcc_rxintr __P((void *));
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extern int clmpcc_txintr __P((void *));
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extern int clmpcc_mdintr __P((void *));
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extern int clmpcc_softintr __P((void *));
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#endif /* __clmpccvar_h */
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