b9eaff9db8
and see if anything responds. if nothing (that's attributable to the PCI IDE controller) responds, then that channel either has no devices on it or has been disabled (via a non-standard mechanism) by the BIOS. If nothing responds, don't map the compat.-mode interrupt or attach the wdc to that channel, because the BIOS is likely to assign that IRQ to a different PCI device. If that happens, the kernel will panic because that device will try to map the IRQ level-triggered, but the compat interrupt will have been mapped edge-triggered. (One possible way around this is to map the compat interrupt edge-triggered, but it's not clear reading the spec that this is correct or desirable.)
513 lines
15 KiB
C
513 lines
15 KiB
C
/* $NetBSD: pciide.c,v 1.6 1998/03/12 23:34:29 cgd Exp $ */
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/*
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* Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Christopher G. Demetriou
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* for the NetBSD Project.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* PCI IDE controller driver.
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*
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* Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD
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* sys/dev/pci/ppb.c, revision 1.16).
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*
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* See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and
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* "Programming Interface for Bus Master IDE Controller, Revision 1.0
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* 5/16/94" from the PCI SIG.
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*
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* XXX Does not yet support DMA (but does map the Bus Master DMA regs).
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*
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* XXX Does not support serializing the two channels for broken (at least
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* XXX according to linux and freebsd) controllers, e.g. CMD PCI0640.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pciidereg.h>
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#include <dev/pci/pciidevar.h>
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#include <dev/ic/wdcreg.h>
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struct pciide_softc {
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struct device sc_dev;
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void *sc_pci_ih; /* PCI interrupt handle */
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int sc_dma_ok; /* bus-master DMA info */
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bus_space_tag_t sc_dma_iot;
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bus_space_handle_t sc_dma_ioh;
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struct pciide_channel { /* per-channel data */
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/* internal bookkeeping */
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int hw_ok; /* hardware mapped & OK? */
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struct device *dev; /* 'wdc' dev attached */
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int compat; /* is it compat? */
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void *ih; /* compat or pci handle */
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/* used by wdc attachment (read-only after init) */
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bus_space_tag_t cmd_iot, ctl_iot;
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bus_space_handle_t cmd_ioh, ctl_ioh;
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/* filled in by wdc attachment (written by wdc attach) */
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int (*ihand) __P((void *));
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void *ihandarg;
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} sc_channels[PCIIDE_NUM_CHANNELS];
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};
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#define PCIIDE_CHANNEL_NAME(chan) ((chan) == 0 ? "primary" : "secondary")
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#ifdef __BROKEN_INDIRECT_CONFIG
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int pciide_match __P((struct device *, void *, void *));
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#else
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int pciide_match __P((struct device *, struct cfdata *, void *));
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#endif
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void pciide_attach __P((struct device *, struct device *, void *));
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struct cfattach pciide_ca = {
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sizeof(struct pciide_softc), pciide_match, pciide_attach
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};
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int pciide_map_channel_compat __P((struct pciide_softc *,
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struct pci_attach_args *, int));
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const char *pciide_compat_channel_probe __P((struct pciide_softc *,
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struct pci_attach_args *, int));
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int pciide_probe_wdc __P((struct pciide_channel *));
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int pciide_map_channel_native __P((struct pciide_softc *,
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struct pci_attach_args *, int));
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int pciide_print __P((void *, const char *pnp));
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int pciide_compat_intr __P((void *));
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int pciide_pci_intr __P((void *));
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#define PCIIDE_PROBE_WDC_DELAY 100 /* 100us each */
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#define PCIIDE_PROBE_WDC_NDELAY 10000 /* wait up to 1s */
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int
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pciide_match(parent, match, aux)
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struct device *parent;
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#ifdef __BROKEN_INDIRECT_CONFIG
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void *match;
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#else
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struct cfdata *match;
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#endif
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void *aux;
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{
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struct pci_attach_args *pa = aux;
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/*
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* Check the ID register to see that it's a PCI IDE controller.
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* If it is, we assume that we can deal with it; it _should_
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* work in a standardized way...
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*/
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if (PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE &&
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PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) {
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return (1);
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}
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return (0);
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}
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void
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pciide_attach(parent, self, aux)
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struct device *parent, *self;
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void *aux;
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{
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struct pci_attach_args *pa = aux;
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pci_chipset_tag_t pc = pa->pa_pc;
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struct pciide_softc *sc = (struct pciide_softc *)self;
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struct pciide_attach_args aa;
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struct pciide_channel *cp;
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pcireg_t class, interface, csr;
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pci_intr_handle_t intrhandle;
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const char *intrstr;
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char devinfo[256];
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int i;
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pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo);
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printf(": %s (rev. 0x%02x)\n", devinfo, PCI_REVISION(pa->pa_class));
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if ((pa->pa_flags & PCI_FLAGS_IO_ENABLED) == 0) {
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csr = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
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printf("%s: device disabled (at %s)\n", sc->sc_dev.dv_xname,
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(csr & PCI_COMMAND_IO_ENABLE) == 0 ? "device" : "bridge");
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return;
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}
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class = pci_conf_read(pc, pa->pa_tag, PCI_CLASS_REG);
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interface = PCI_INTERFACE(class);
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/*
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* Set up PCI interrupt.
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*
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* If mapping fails, that's (probably) because there's no pin
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* set to intr, which is (probably) because it's a compat-only
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* device (or hard-wired in compatibility-only mode). Native-PCI
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* channels will complain later if the interrupt was needed.
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*
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* If establishment fails, that's (probably) some other problem.
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*/
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if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin,
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pa->pa_intrline, &intrhandle) == 0) {
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intrstr = pci_intr_string(pa->pa_pc, intrhandle);
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sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, intrhandle,
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IPL_BIO, pciide_pci_intr, sc);
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if (sc->sc_pci_ih != NULL) {
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printf("%s: using %s for native-PCI interrupt\n",
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sc->sc_dev.dv_xname,
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intrstr ? intrstr : "unknown interrupt");
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} else {
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printf("%s: couldn't establish native-PCI interrupt",
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sc->sc_dev.dv_xname);
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if (intrstr != NULL)
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printf(" at %s", intrstr);
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printf("\n");
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}
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}
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/*
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* Map DMA registers, if DMA is supported.
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*
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* Note that sc_dma_ok is the right variable to test to see if
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* DMA can * be done. If the interface doesn't support DMA,
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* sc_dma_ok * will never be non-zero. If the DMA regs couldn't
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* be mapped, it'll be zero. I.e., sc_dma_ok will only be
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* non-zero if the interface supports DMA and the registers
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* could be mapped.
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*
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* XXX Note that despite the fact that the Bus Master IDE specs
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* XXX say that "The bus master IDE functoin uses 16 bytes of IO
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* XXX space," some controllers (at least the United
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* XXX Microelectronics UM8886BF) place it in memory space.
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* XXX eventually, we should probably read the register and check
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* XXX which type it is. Either that or 'quirk' certain devices.
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*/
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if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) {
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sc->sc_dma_ok = (pci_mapreg_map(pa,
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PCIIDE_REG_BUS_MASTER_DMA, PCI_MAPREG_TYPE_IO, 0,
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&sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, NULL) == 0);
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printf("%s: bus-master DMA support present, but unused (%s)\n",
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sc->sc_dev.dv_xname,
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sc->sc_dma_ok ? "no driver support" :
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"couldn't map registers");
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}
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for (i = 0; i < PCIIDE_NUM_CHANNELS; i++) {
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cp = &sc->sc_channels[i];
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printf("%s: %s channel %s to %s mode\n",
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sc->sc_dev.dv_xname, PCIIDE_CHANNEL_NAME(i),
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(interface & PCIIDE_INTERFACE_SETTABLE(i)) ?
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"configured" : "wired",
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(interface & PCIIDE_INTERFACE_PCI(i)) ? "native-PCI" :
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"compatibility");
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if (interface & PCIIDE_INTERFACE_PCI(i))
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cp->hw_ok = pciide_map_channel_native(sc, pa, i);
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else
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cp->hw_ok = pciide_map_channel_compat(sc, pa, i);
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if (!cp->hw_ok)
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continue;
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aa.channel = i;
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aa.cmd_iot = cp->cmd_iot;
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aa.cmd_ioh = cp->cmd_ioh;
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aa.ctl_iot = cp->ctl_iot;
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aa.ctl_ioh = cp->ctl_ioh;
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aa.ihandp = &cp->ihand;
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aa.ihandargp = &cp->ihandarg;
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cp->dev = config_found(self, &aa, pciide_print);
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/*
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* Note that if the 'wdc' device isn't configured,
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* the controller's resources are still marked as
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* being in use. This is a feature.
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*/
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}
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}
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int
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pciide_map_channel_compat(sc, pa, chan)
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struct pciide_softc *sc;
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struct pci_attach_args *pa;
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int chan;
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{
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struct pciide_channel *cp = &sc->sc_channels[chan];
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const char *probe_fail_reason;
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int rv = 1;
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cp->compat = 1;
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cp->cmd_iot = pa->pa_iot;
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if (bus_space_map(cp->cmd_iot, PCIIDE_COMPAT_CMD_BASE(chan),
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PCIIDE_COMPAT_CMD_SIZE, 0, &cp->cmd_ioh) != 0) {
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printf("%s: couldn't map %s channel cmd regs\n",
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sc->sc_dev.dv_xname, PCIIDE_CHANNEL_NAME(chan));
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rv = 0;
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}
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cp->ctl_iot = pa->pa_iot;
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if (bus_space_map(cp->ctl_iot, PCIIDE_COMPAT_CTL_BASE(chan),
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PCIIDE_COMPAT_CTL_SIZE, 0, &cp->ctl_ioh) != 0) {
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printf("%s: couldn't map %s channel ctl regs\n",
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sc->sc_dev.dv_xname, PCIIDE_CHANNEL_NAME(chan));
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rv = 0;
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}
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/*
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* If we weren't able to map the device successfully,
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* we just give up now. Something else has already
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* occupied those ports, indicating that the device has
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* (probably) been completely disabled (by some nonstandard
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* mechanism).
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*
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* XXX If we successfully map some ports, but not others,
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* XXX it might make sense to unmap the ones that we mapped.
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*/
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if (rv == 0)
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goto out;
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/*
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* If we were able to map the device successfully, try to
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* make sure that there's a wdc there and that it's
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* attributable to us.
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*
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* If there's not, then we assume that there's the device
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* has been disabled and that other devices are free to use
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* its ports.
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*/
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probe_fail_reason = pciide_compat_channel_probe(sc, pa, chan);
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if (probe_fail_reason != NULL) {
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printf("%s: %s channel ignored (%s)\n", sc->sc_dev.dv_xname,
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PCIIDE_CHANNEL_NAME(chan), probe_fail_reason);
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rv = 0;
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bus_space_unmap(cp->cmd_iot, cp->cmd_ioh,
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PCIIDE_COMPAT_CMD_SIZE);
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bus_space_unmap(cp->ctl_iot, cp->ctl_ioh,
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PCIIDE_COMPAT_CTL_SIZE);
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goto out;
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}
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/*
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* If we're here, we were able to map the device successfully
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* and it really looks like there's a controller there.
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*
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* Unless those conditions are true, we don't map the
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* compatibility interrupt. The spec indicates that if a
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* channel is configured for compatibility mode and the PCI
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* device's I/O space is enabled, the channel will be enabled.
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* Hoewver, some devices seem to be able to disable invididual
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* compatibility channels (via non-standard mechanisms). If
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* the channel is disabled, the interrupt line can (probably)
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* be used by other devices (and may be assigned to other
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* devices by the BIOS). If we mapped the interrupt we might
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* conflict with another interrupt assignment.
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*/
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cp->ih = pciide_machdep_compat_intr_establish(&sc->sc_dev, pa,
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chan, pciide_compat_intr, cp);
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if (cp->ih == NULL) {
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printf("%s: no compatibility interrupt for use by %s channel\n",
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sc->sc_dev.dv_xname, PCIIDE_CHANNEL_NAME(chan));
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rv = 0;
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}
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out:
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return (rv);
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}
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const char *
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pciide_compat_channel_probe(sc, pa, chan)
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struct pciide_softc *sc;
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struct pci_attach_args *pa;
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{
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pcireg_t csr;
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const char *failreason = NULL;
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/*
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* Check to see if something appears to be there.
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*/
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if (!pciide_probe_wdc(&sc->sc_channels[chan])) {
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failreason = "not responding; disabled or no drives?";
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goto out;
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}
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/*
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* Now, make sure it's actually attributable to this PCI IDE
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* channel by trying to access the channel again while the
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* PCI IDE controller's I/O space is disabled. (If the
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* channel no longer appears to be there, it belongs to
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* this controller.) YUCK!
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*/
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csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
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pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
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csr & ~PCI_COMMAND_IO_ENABLE);
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if (pciide_probe_wdc(&sc->sc_channels[chan]))
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failreason = "other hardware responding at addresses";
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pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, csr);
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out:
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return (failreason);
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}
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int
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pciide_probe_wdc(cp)
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struct pciide_channel *cp;
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{
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u_int8_t st0, st1;
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int timeout;
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/*
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* Sanity check to see if the wdc channel responds at all.
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* (Modeled on wdc_init_controller() and wdc_reset() in wdc.c.)
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*
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* Reset the channel, and make sure that it responds sanely
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* after it's been reset.
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*/
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/* Reset the channel. */
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bus_space_write_1(cp->ctl_iot, cp->ctl_ioh, wd_aux_ctlr,
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WDCTL_RST | WDCTL_IDS);
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delay(1000);
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bus_space_write_1(cp->ctl_iot, cp->ctl_ioh, wd_aux_ctlr,
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WDCTL_IDS);
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delay(1000);
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(void)bus_space_read_1(cp->cmd_iot, cp->cmd_ioh, wd_error);
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timeout = 0;
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while (timeout++ < PCIIDE_PROBE_WDC_NDELAY) {
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st0 = bus_space_read_1(cp->cmd_iot, cp->cmd_ioh, wd_status);
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bus_space_write_1(cp->cmd_iot, cp->cmd_ioh, wd_sdh,
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WDSD_IBM | 0x10);
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st1 = bus_space_read_1(cp->cmd_iot, cp->cmd_ioh, wd_status);
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if ((st0 & WDCS_BSY) == 0 || (st1 & WDCS_BSY) == 0)
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return (1);
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delay(PCIIDE_PROBE_WDC_DELAY);
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}
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/* timed out; nothing there */
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return (0);
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}
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int
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pciide_map_channel_native(sc, pa, chan)
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struct pciide_softc *sc;
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struct pci_attach_args *pa;
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int chan;
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{
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struct pciide_channel *cp = &sc->sc_channels[chan];
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int rv = 1;
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cp->compat = 0;
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if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(chan), PCI_MAPREG_TYPE_IO,
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0, &cp->cmd_iot, &cp->cmd_ioh, NULL, NULL) != 0) {
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printf("%s: couldn't map %s channel cmd regs\n",
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sc->sc_dev.dv_xname, PCIIDE_CHANNEL_NAME(chan));
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rv = 0;
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}
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if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(chan), PCI_MAPREG_TYPE_IO,
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0, &cp->ctl_iot, &cp->ctl_ioh, NULL, NULL) != 0) {
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printf("%s: couldn't map %s channel ctl regs\n",
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sc->sc_dev.dv_xname, PCIIDE_CHANNEL_NAME(chan));
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rv = 0;
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}
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if ((cp->ih = sc->sc_pci_ih) == NULL) {
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printf("%s: no native-PCI interrupt for use by %s channel\n",
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sc->sc_dev.dv_xname, PCIIDE_CHANNEL_NAME(chan));
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rv = 0;
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}
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return (rv);
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}
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|
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int
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pciide_print(aux, pnp)
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void *aux;
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const char *pnp;
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{
|
|
struct pciide_attach_args *aa = aux;
|
|
|
|
/* only 'wdc's can attach to 'pciide's; easy. */
|
|
if (pnp)
|
|
printf("wdc at %s", pnp);
|
|
printf(" channel %d", aa->channel);
|
|
return (UNCONF);
|
|
}
|
|
|
|
int
|
|
pciide_compat_intr(arg)
|
|
void *arg;
|
|
{
|
|
struct pciide_channel *cp = arg;
|
|
|
|
#ifdef DIAGNOSTIC
|
|
/* should only be called for a compat channel */
|
|
if (cp->compat == 0)
|
|
panic("pciide compat intr called for non-compat chan %p\n", cp);
|
|
#endif
|
|
/* if there's no handler, that probably means no dev attached */
|
|
if (cp->ihand == NULL)
|
|
return (0);
|
|
|
|
return ((*cp->ihand)(cp->ihandarg));
|
|
}
|
|
|
|
int
|
|
pciide_pci_intr(arg)
|
|
void *arg;
|
|
{
|
|
struct pciide_softc *sc = arg;
|
|
struct pciide_channel *cp;
|
|
int i, rv, crv;
|
|
|
|
rv = 0;
|
|
for (i = 0; i < PCIIDE_NUM_CHANNELS; i++) {
|
|
cp = &sc->sc_channels[i];
|
|
|
|
/* If a compat channel or there's no handler, skip. */
|
|
if (cp->compat || cp->ihand == NULL)
|
|
continue;
|
|
|
|
crv = ((*cp->ihand)(cp->ihandarg));
|
|
if (crv == 0)
|
|
; /* leave rv alone */
|
|
else if (crv == 1)
|
|
rv = 1; /* claim the intr */
|
|
else if (rv == 0) /* crv should be -1 in this case */
|
|
rv = crv; /* if we've done no better, take it */
|
|
}
|
|
return (rv);
|
|
}
|