131 lines
4.1 KiB
C
131 lines
4.1 KiB
C
/* $NetBSD: iq80321reg.h,v 1.1 2002/03/27 21:51:30 thorpej Exp $ */
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/*
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* Copyright (c) 2002 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Jason R. Thorpe for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _IQ80321REG_H_
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#define _IQ80321REG_H_
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/*
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* Memory map and register definitions for the Intel IQ80321
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* Evaluation Board.
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*/
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/*
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* The memory map of the IQ80321 looks like so:
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*
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* ------------------------------
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* Intel 80321 IOP Reserved
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* FFFF E900 ------------------------------
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* Peripheral Memory Mapped
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* Registers
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* FFFF E000 ------------------------------
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* On-board devices
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* FE80 0000 ------------------------------
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* SDRAM
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* A000 0000 ------------------------------
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* Reserved
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* 9100 0000 ------------------------------
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* Flash
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* 9080 0000 ------------------------------
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* Reserved
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* 9002 0000 ------------------------------
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* ATU Outbound Transaction
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* Windows
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* 8000 0000 ------------------------------
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* ATU Outbound Direct
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* Addressing Windows
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* 0000 1000 ------------------------------
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* Initialization Boot Code
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* from Flash
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* 0000 0000 ------------------------------
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*/
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/*
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* We allocate a page table for VA 0xfe400000 (4MB) and map the
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* PCI I/O space (64K) and i80321 memory-mapped registers (4K) there.
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*/
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#define IQ80321_IOPXS_VBASE 0xfe400000UL
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#define IQ80321_IOW_VBASE IQ80321_IOPXS_VBASE
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#define IQ80321_80321_VBASE (IQ80321_IOW_VBASE + \
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VERDE_OUT_XLATE_IO_WIN_SIZE)
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/*
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* The IQ80321 on-board devices are mapped VA==PA during bootstrap.
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* Conveniently, the size of the on-board register space is 1 section
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* mapping.
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*/
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#define IQ80321_OBIO_BASE 0xfe800000UL
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#define IQ80321_OBIO_SIZE 0x00100000UL /* 1MB */
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#define IQ80321_UART1 0xfe800000UL /* TI 16550 */
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#define IQ80321_7SEG_MSB 0xfe840000UL
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#define IQ80321_7SEG_LSB 0xfe850000UL
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/*
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* The 7-segment display looks like so:
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*
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* A
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* +-----+
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* | |
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* F | | B
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* | G |
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* +-----+
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* | |
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* E | | C
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* | D |
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* +-----+ o DP
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*
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* Setting a bit clears the corresponding segment on the
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* display.
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*/
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#define SEG_A (1 << 7)
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#define SEG_B (1 << 6)
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#define SEG_C (1 << 5)
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#define SEG_D (1 << 4)
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#define SEG_E (1 << 3)
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#define SEG_F (1 << 2)
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#define SEG_G (1 << 1)
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#define SEG_DP (1 << 0)
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#define IQ80321_ROT_SWITCH 0xfe8d0000UL
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#define IQ80321_BATTERY_STAT 0xfe8f0000UL
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#define BATTERY_STAT_PRES (1U << 0)
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#define BATTERY_STAT_CHRG (1U << 1)
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#define BATTERY_STAT_DISCHRG (1U << 2)
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#endif /* _IQ80321REG_H_ */
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