337 lines
9.5 KiB
C
337 lines
9.5 KiB
C
/* $NetBSD: if_rl_cardbus.c,v 1.2 2000/04/11 06:57:59 haya Exp $ */
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/*
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* Copyright (c) 2000 Masanori Kanaoka
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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/*
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* if_rl_cardbus.c:
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* Cardbus specific routines for RealTek 8139 ethernet adapter.
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* Tested for
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* - elecom-Laneed LD-10/100CBA (Accton MPX5030)
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* - MELCO LPC3-TX-CB (RealTek 8138)
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*/
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#include "opt_inet.h"
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#include "opt_ns.h"
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#include "bpfilter.h"
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#include "rnd.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/callout.h>
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#include <sys/device.h>
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#include <sys/sockio.h>
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#include <sys/mbuf.h>
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#include <sys/malloc.h>
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#include <sys/kernel.h>
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#include <sys/socket.h>
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#include <net/if.h>
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#include <net/if_arp.h>
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#include <net/if_ether.h>
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#include <net/if_dl.h>
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#include <net/if_media.h>
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#ifdef INET
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#include <netinet/in.h>
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#include <netinet/if_inarp.h>
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#endif
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#ifdef NS
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#include <netns/ns.h>
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#include <netns/ns_if.h>
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#endif
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#if NBPFILTER > 0
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#include <net/bpf.h>
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#endif
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#if NRND > 0
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#include <sys/rnd.h>
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#endif
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#include <machine/bus.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcidevs.h>
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#include <dev/cardbus/cardbusvar.h>
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#include <dev/cardbus/cardbusdevs.h>
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#include <dev/mii/mii.h>
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#include <dev/mii/miivar.h>
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/*
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* Default to using PIO access for this driver. On SMP systems,
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* there appear to be problems with memory mapped mode: it looks like
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* doing too many memory mapped access back to back in rapid succession
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* can hang the bus. I'm inclined to blame this on crummy design/construction
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* on the part of RealTek. Memory mapped mode does appear to work on
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* uniprocessor systems though.
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*/
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#define RL_USEIOSPACE
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#include <dev/ic/rtl81x9reg.h>
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/*
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* Various supported device vendors/types and their names.
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*/
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static struct rl_type rl_cardbus_devs[] = {
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{ CARDBUS_VENDOR_ACCTON, CARDBUS_PRODUCT_ACCTON_MPX5030,
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"Accton MPX 5030/5038 10/100BaseTX" },
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{ CARDBUS_VENDOR_REALTEK, CARDBUS_PRODUCT_REALTEK_RT8138,
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"RealTek 8138 10/100BaseTX" },
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{ 0, 0, NULL }
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};
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const struct rl_type *rl_cardbus_lookup
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__P((const struct cardbus_attach_args *));
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static int rl_cardbus_match __P((struct device *, struct cfdata *, void *));
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static void rl_cardbus_attach __P((struct device *, struct device *, void *));
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struct rl_cardbus_softc {
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struct rl_softc sc_rl; /* real rl softc */
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/* CardBus-specific goo. */
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void *sc_ih;
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cardbus_devfunc_t sc_ct;
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cardbustag_t sc_tag;
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int sc_csr;
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int sc_cben;
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int sc_bar_reg;
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pcireg_t sc_bar_val;
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bus_size_t sc_mapsize;
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int sc_intrline;
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};
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struct cfattach rl_cardbus_ca = {
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sizeof(struct rl_cardbus_softc), rl_cardbus_match, rl_cardbus_attach,
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};
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const struct rl_type *
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rl_cardbus_lookup(ca)
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const struct cardbus_attach_args *ca;
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{
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struct rl_type *t;
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for (t = rl_cardbus_devs; t->rl_name != NULL; t++){
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if (PCI_VENDOR(ca->ca_id) == t->rl_vid &&
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PCI_PRODUCT(ca->ca_id) == t->rl_did) {
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return (t);
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}
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}
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return (NULL);
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}
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int
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rl_cardbus_match(parent, match, aux)
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struct device *parent;
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struct cfdata *match;
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void *aux;
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{
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struct cardbus_attach_args *ca = aux;
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if (rl_cardbus_lookup(ca) != NULL)
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return (1);
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return (0);
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}
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void
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rl_cardbus_attach(parent, self, aux)
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struct device *parent, *self;
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void *aux;
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{
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int s;
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#ifndef RL_USEIOSPACE
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vm_offset_t pbase, vbase;
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#endif
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u_char eaddr[ETHER_ADDR_LEN];
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u_int32_t command;
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struct rl_cardbus_softc *csc = (struct rl_cardbus_softc *)self;
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struct rl_softc *sc = &csc->sc_rl;
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struct cardbus_attach_args *ca = aux;
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cardbus_devfunc_t ct = ca->ca_ct;
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cardbus_chipset_tag_t cc = ct->ct_cc;
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cardbus_function_tag_t cf = ct->ct_cf;
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const struct rl_type *t;
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bus_addr_t adr;
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pcireg_t reg;
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sc->sc_dmat = ca->ca_dmat;
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csc->sc_ct = ct;
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csc->sc_tag = ca->ca_tag;
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csc->sc_intrline = ca->ca_intrline;
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t = rl_cardbus_lookup(ca);
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if (t == NULL) {
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printf("\n");
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panic("rl_cardbus_attach: impossible");
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}
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printf(": %s\n", t->rl_name);
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s = splimp();
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/*
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* Handle power management nonsense.
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*/
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if (cardbus_get_capability(cc, cf, csc->sc_tag, PCI_CAP_PWRMGMT, 0, 0)) {
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command = cardbus_conf_read(cc, cf, csc->sc_tag, RL_PCI_PWRMGMTCTRL);
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if (command & RL_PSTATE_MASK) {
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u_int32_t iobase, membase, irq;
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/* Save important PCI config data. */
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iobase = cardbus_conf_read(cc, cf, csc->sc_tag, RL_PCI_LOIO);
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membase = cardbus_conf_read(cc, cf,csc->sc_tag, RL_PCI_LOMEM);
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irq = cardbus_conf_read(cc, cf,csc->sc_tag, PCI_PRODUCT_DELTA_8139);
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/* Reset the power state. */
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printf("%s: chip is is in D%d power mode "
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"-- setting to D0\n", sc->sc_dev.dv_xname,
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command & RL_PSTATE_MASK);
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command &= 0xFFFFFFFC;
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cardbus_conf_write(cc, cf, csc->sc_tag, RL_PCI_PWRMGMTCTRL, command);
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/* Restore PCI config data. */
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cardbus_conf_write(cc, cf, csc->sc_tag, RL_PCI_LOIO, iobase);
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cardbus_conf_write(cc, cf, csc->sc_tag, RL_PCI_LOMEM, membase);
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cardbus_conf_write(cc, cf, csc->sc_tag, PCI_PRODUCT_DELTA_8139, irq);
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}
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}
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/*
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* Map control/status registers.
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*/
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#ifdef RL_USEIOSPACE
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if (Cardbus_mapreg_map(ct, RL_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0,
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&sc->rl_btag, &sc->rl_bhandle, &adr, &csc->sc_mapsize) == 0) {
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#if rbus
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#else
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(*ct->ct_cf->carbus_io_open)(cc,0,adr, adr+csc->sc_mapsize);
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#endif
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csc->sc_cben = CARDBUS_IO_ENABLE;
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csc->sc_csr |= (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE);
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csc->sc_bar_reg = RL_PCI_LOIO;
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csc->sc_bar_val = adr | PCI_MAPREG_TYPE_IO;
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}
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#else
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if (Cardbus_mapreg_map(ct, RL_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0,
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&sc->rl_btag, &sc->rl_bhandle, &adr, &csc->sc_mapsize) == 0) {
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#if rbus
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#else
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(*ct->ct_cf->carbus_mem_open)(cc,0,adr, adr+csc->sc_mapsize);
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#endif
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csc->sc_cben = CARDBUS_MEM_ENABLE;
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csc->sc_csr |= (PCI_COMMAND_MEM_ENABLE|PCI_COMMAND_MASTER_ENABLE);
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csc->sc_bar_reg = RL_PCI_LOMEM;
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csc->sc_bar_val = adr | PCI_MAPREG_TYPE_MEM;
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}
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#endif
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else {
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printf(": can't map i/o space\n");
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goto fail;
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}
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/* Make sure the right access type is on the CardBus bridge. */
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(*ct->ct_cf->cardbus_ctrl)(cc,csc->sc_cben);
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(*ct->ct_cf->cardbus_ctrl)(cc,CARDBUS_BM_ENABLE);
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/* Program the BAR */
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cardbus_conf_write(cc, cf, csc->sc_tag,
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csc->sc_bar_reg, csc->sc_bar_val);
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/* Enable the appropriate bits in the PCI CSR. */
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reg = cardbus_conf_read(cc, cf, csc->sc_tag, PCI_COMMAND_STATUS_REG);
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reg &= ~(PCI_COMMAND_IO_ENABLE|PCI_COMMAND_MEM_ENABLE);
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reg |= csc->sc_csr;
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cardbus_conf_write(cc, cf, csc->sc_tag, PCI_COMMAND_STATUS_REG,reg);
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/*
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* Make sure the latency timer is set to some reasonable
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* value.
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*/
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reg = cardbus_conf_read(cc, cf, csc->sc_tag, PCI_BHLC_REG);
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if (PCI_LATTIMER(reg) < 0x20) {
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reg &= ~(PCI_LATTIMER_MASK << PCI_LATTIMER_SHIFT);
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reg |= (0x20 << PCI_LATTIMER_SHIFT);
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cardbus_conf_write(cc, cf, csc->sc_tag, PCI_BHLC_REG, reg);
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}
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/* Reset the adapter. */
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rl_reset(sc);
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/*
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* Now read the exact device type from the EEPROM to find
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* out if it's an 8129 or 8139.
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*/
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if (t->rl_did == CARDBUS_PRODUCT_ACCTON_MPX5030 ||
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t->rl_did == CARDBUS_PRODUCT_REALTEK_RT8138){
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sc->rl_type = RL_8139;
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/*
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* LD-10/100CBA (ACCTON_MPX5030):
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* LPC3-TX-CB (REALTEK_RT8138):
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* rl_read_eeprom() can't get MAC address
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* from EEPROM(serial access). Lift MAC address
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* from RL-IDR0 -Rl_IDR5 register.
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*
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* RTL8139B(L) datasheet rev 2.4.
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*
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* o REGSTER RL_IDR0 - RL_IDR5 address
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*
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* o "After the vaild duration of the RSTB pin or
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* autoload command in 9346CR,RTL8139B(L) performs
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* a series of EEPROM read operation from 93C46(93C56)
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* address 00H to 31H." from 6. EEPROM Contents
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*/
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eaddr[0] = CSR_READ_1(sc, RL_IDR0);
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eaddr[1] = CSR_READ_1(sc, RL_IDR1);
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eaddr[2] = CSR_READ_1(sc, RL_IDR2);
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eaddr[3] = CSR_READ_1(sc, RL_IDR3);
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eaddr[4] = CSR_READ_1(sc, RL_IDR4);
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eaddr[5] = CSR_READ_1(sc, RL_IDR5);
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} else {
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printf(": unknown device ID: 0x%x\n", t->rl_did);
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goto fail;
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}
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printf("%s: Ethernet address: %s\n", sc->sc_dev.dv_xname,
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ether_sprintf(eaddr));
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/* Allocate interrupt */
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printf("%s: interrupting at %d\n", sc->sc_dev.dv_xname, csc->sc_intrline);
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csc->sc_ih = cardbus_intr_establish(cc, cf, csc->sc_intrline, IPL_NET,
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rl_intr, sc);
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if (csc->sc_ih == NULL) {
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printf("%s: unable to establish interrupt at %d\n",
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sc->sc_dev.dv_xname,csc->sc_intrline);
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printf("\n");
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goto fail;
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}
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rl_attach(sc, eaddr);
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fail:
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splx(s);
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return;
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}
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