494 lines
13 KiB
C
494 lines
13 KiB
C
/* $NetBSD: locore.h,v 1.80 2009/12/14 00:46:04 matt Exp $ */
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/*
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* Copyright 1996 The Board of Trustees of The Leland Stanford
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* Junior University. All Rights Reserved.
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*
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* Permission to use, copy, modify, and distribute this
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* software and its documentation for any purpose and without
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* fee is hereby granted, provided that the above copyright
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* notice appear in all copies. Stanford University
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* makes no representations about the suitability of this
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* software for any purpose. It is provided "as is" without
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* express or implied warranty.
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*/
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/*
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* Jump table for MIPS CPU locore functions that are implemented
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* differently on different generations, or instruction-level
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* archtecture (ISA) level, the Mips family.
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*
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* We currently provide support for MIPS I and MIPS III.
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*/
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#ifndef _MIPS_LOCORE_H
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#define _MIPS_LOCORE_H
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#ifndef _LKM
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#include "opt_cputype.h"
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#endif
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#include <mips/cpuregs.h>
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struct tlb;
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uint32_t mips_cp0_cause_read(void);
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void mips_cp0_cause_write(uint32_t);
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uint32_t mips_cp0_status_read(void);
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void mips_cp0_status_write(uint32_t);
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int _splraise(int);
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int _spllower(int);
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int _splset(int);
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int _splget(void);
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void _splnone(void);
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void _setsoftintr(int);
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void _clrsoftintr(int);
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#ifdef MIPS1
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void mips1_SetPID(int);
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void mips1_TBIA(int);
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void mips1_TBIAP(int);
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void mips1_TBIS(vaddr_t);
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int mips1_TLBUpdate(vaddr_t, uint32_t);
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void mips1_wbflush(void);
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void mips1_lwp_trampoline(void);
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void mips1_setfunc_trampoline(void);
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void mips1_cpu_switch_resume(void);
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uint32_t tx3900_cp0_config_read(void);
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#endif
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#if defined(MIPS3) || defined(MIPS4)
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void mips3_SetPID(int);
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void mips3_TBIA(int);
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void mips3_TBIAP(int);
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void mips3_TBIS(vaddr_t);
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int mips3_TLBUpdate(vaddr_t, uint32_t);
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void mips3_TLBRead(int, struct tlb *);
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void mips3_TLBWriteIndexedVPS(int, struct tlb *);
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void mips3_wbflush(void);
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void mips3_lwp_trampoline(void);
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void mips3_setfunc_trampoline(void);
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void mips3_cpu_switch_resume(void);
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void mips3_pagezero(void *dst);
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#ifdef MIPS3_5900
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void mips5900_SetPID(int);
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void mips5900_TBIA(int);
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void mips5900_TBIAP(int);
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void mips5900_TBIS(vaddr_t);
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int mips5900_TLBUpdate(vaddr_t, uint32_t);
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void mips5900_TLBRead(int, struct tlb *);
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void mips5900_TLBWriteIndexedVPS(int, struct tlb *);
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void mips5900_wbflush(void);
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void mips5900_lwp_trampoline(void);
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void mips5900_setfunc_trampoline(void);
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void mips5900_cpu_switch_resume(void);
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void mips5900_pagezero(void *dst);
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#endif
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#endif
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#ifdef MIPS32
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void mips32_SetPID(int);
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void mips32_TBIA(int);
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void mips32_TBIAP(int);
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void mips32_TBIS(vaddr_t);
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int mips32_TLBUpdate(vaddr_t, uint32_t);
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void mips32_TLBRead(int, struct tlb *);
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void mips32_TLBWriteIndexedVPS(int, struct tlb *);
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void mips32_wbflush(void);
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void mips32_lwp_trampoline(void);
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void mips32_setfunc_trampoline(void);
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void mips32_cpu_switch_resume(void);
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#endif
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#ifdef MIPS64
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void mips64_SetPID(int);
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void mips64_TBIA(int);
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void mips64_TBIAP(int);
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void mips64_TBIS(vaddr_t);
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int mips64_TLBUpdate(vaddr_t, uint32_t);
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void mips64_TLBRead(int, struct tlb *);
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void mips64_TLBWriteIndexedVPS(int, struct tlb *);
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void mips64_wbflush(void);
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void mips64_lwp_trampoline(void);
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void mips64_setfunc_trampoline(void);
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void mips64_cpu_switch_resume(void);
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void mips64_pagezero(void *dst);
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#endif
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#if defined(MIPS3) || defined(MIPS4) || defined(MIPS32) || defined(MIPS64)
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uint32_t mips3_cp0_compare_read(void);
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void mips3_cp0_compare_write(uint32_t);
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uint32_t mips3_cp0_config_read(void);
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void mips3_cp0_config_write(uint32_t);
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#if defined(MIPS32) || defined(MIPS64)
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uint32_t mipsNN_cp0_config1_read(void);
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void mipsNN_cp0_config1_write(uint32_t);
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uint32_t mipsNN_cp0_config2_read(void);
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uint32_t mipsNN_cp0_config3_read(void);
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#endif
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uint32_t mips3_cp0_count_read(void);
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void mips3_cp0_count_write(uint32_t);
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uint32_t mips3_cp0_wired_read(void);
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void mips3_cp0_wired_write(uint32_t);
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void mips3_cp0_pg_mask_write(uint32_t);
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#if defined(__GNUC__) && !defined(__mips_o32)
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static inline uint64_t
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mips3_ld(const volatile uint64_t *va)
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{
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uint64_t rv;
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#if defined(__mips_o32)
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uint32_t sr;
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sr = mips_cp0_status_read();
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mips_cp0_status_write(sr & ~MIPS_SR_INT_IE);
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__asm volatile(
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".set push \n\t"
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".set mips3 \n\t"
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".set noreorder \n\t"
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".set noat \n\t"
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"ld %M0,0(%1) \n\t"
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"dsll32 %L0,%M0,0 \n\t"
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"dsra32 %M0,%M0,0 \n\t" /* high word */
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"dsra32 %L0,%L0,0 \n\t" /* low word */
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"ld %0,0(%1) \n\t"
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".set pop"
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: "=d"(rv)
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: "r"(va));
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mips_cp0_status_write(sr);
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#elif defined(_LP64)
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rv = *va;
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#else
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__asm volatile("ld %0,0(%1)" : "=d"(rv) : "r"(va));
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#endif
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return rv;
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}
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static inline void
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mips3_sd(volatile uint64_t *va, uint64_t v)
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{
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#if defined(__mips_o32)
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uint32_t sr;
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sr = mips_cp0_status_read();
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mips_cp0_status_write(sr & ~MIPS_SR_INT_IE);
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__asm volatile(
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".set push \n\t"
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".set mips3 \n\t"
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".set noreorder \n\t"
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".set noat \n\t"
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"dsll32 %M0,%M0,0 \n\t"
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"dsll32 %L0,%L0,0 \n\t"
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"dsrl32 %L0,%L0,0 \n\t"
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"or %0,%L0,%M0 \n\t"
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"sd %0,0(%1) \n\t"
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".set pop"
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: "=d"(v) : "0"(v), "r"(va));
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mips_cp0_status_write(sr);
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#elif defined(_LP64)
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*va = v;
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#else
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__asm volatile("sd %0,0(%1)" :: "r"(v), "r"(va));
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#endif
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}
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#else
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uint64_t mips3_ld(volatile uint64_t *va);
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void mips3_sd(volatile uint64_t *, uint64_t);
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#endif /* __GNUC__ */
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#endif /* MIPS3 || MIPS4 || MIPS32 || MIPS64 */
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#if defined(MIPS3) || defined(MIPS4) || defined(MIPS64)
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static __inline uint32_t mips3_lw_a64(uint64_t addr)
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__attribute__((__unused__));
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static __inline void mips3_sw_a64(uint64_t addr, uint32_t val)
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__attribute__ ((__unused__));
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static __inline uint32_t
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mips3_lw_a64(uint64_t addr)
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{
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uint32_t rv;
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#if defined(__mips_o32)
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uint32_t sr;
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sr = mips_cp0_status_read();
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mips_cp0_status_write((sr & ~MIPS_SR_INT_IE) | MIPS3_SR_KX);
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__asm volatile (
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".set push \n\t"
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".set mips3 \n\t"
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".set noreorder \n\t"
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".set noat \n\t"
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"dsll32 %M1,%M1,0 \n\t"
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"dsll32 %L1,%L1,0 \n\t"
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"dsrl32 $L1,%L1,0 \n\t"
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"or %1,%M1,%L1 \n\t"
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"lw %0, 0(%1) \n\t"
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".set pop"
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: "=r"(rv), "=d"(addr)
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: "1"(addr)
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);
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mips_cp0_status_write(sr);
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#elif defined(_LP64)
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rv = *(const uint32_t *)addr;
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#else
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__asm volatile("lw %0, 0(%1)" : "=r"(rv) : "d"(addr));
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#endif
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return (rv);
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}
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static __inline void
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mips3_sw_a64(uint64_t addr, uint32_t val)
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{
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#if defined(__mips_o32)
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uint32_t sr;
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sr = mips_cp0_status_read();
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mips_cp0_status_write((sr & ~MIPS_SR_INT_IE) | MIPS3_SR_KX);
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__asm volatile (
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".set push \n\t"
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".set mips3 \n\t"
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".set noreorder \n\t"
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".set noat \n\t"
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"dsll32 %M0,%M0,0 \n\t"
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"dsll32 %L0,%L0,0 \n\t"
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"dsrl32 $L0,%L0,0 \n\t"
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"or %0,%M0,%L0 \n\t"
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"sw %1, 0(%0) \n\t"
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".set pop"
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: "=d"(addr): "r"(val), "0"(addr)
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);
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mips_cp0_status_write(sr);
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#elif defined(_LP64)
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*(uint32_t *)addr = val;
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#else
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__asm volatile("sw %1, 0(%0)" :: "d"(addr), "r"(val));
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#endif
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}
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#endif /* MIPS3 || MIPS4 || MIPS64 */
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/*
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* A vector with an entry for each mips-ISA-level dependent
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* locore function, and macros which jump through it.
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*
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* XXX the macro names are chosen to be compatible with the old
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* XXX Sprite coding-convention names used in 4.4bsd/pmax.
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*/
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typedef struct {
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void (*setTLBpid)(int pid);
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void (*TBIAP)(int);
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void (*TBIS)(vaddr_t);
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int (*tlbUpdate)(vaddr_t, uint32_t);
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void (*wbflush)(void);
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} mips_locore_jumpvec_t;
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void mips_set_wbflush(void (*)(void));
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void mips_wait_idle(void);
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void stacktrace(void);
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void logstacktrace(void);
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struct locoresw {
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uintptr_t lsw_cpu_switch_resume;
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uintptr_t lsw_lwp_trampoline;
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void (*lsw_cpu_idle)(void);
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uintptr_t lsw_setfunc_trampoline;
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};
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/*
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* The "active" locore-fuction vector, and
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*/
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extern mips_locore_jumpvec_t mips_locore_jumpvec;
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extern struct locoresw mips_locoresw;
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#if defined(MIPS1) && !defined(MIPS3) && !defined(MIPS32) && !defined(MIPS64)
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#define MachSetPID mips1_SetPID
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#define MIPS_TBIAP() mips1_TBIAP(mips_num_tlb_entries)
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#define MIPS_TBIS mips1_TBIS
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#define MachTLBUpdate mips1_TLBUpdate
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#define wbflush() mips1_wbflush()
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#define lwp_trampoline mips1_lwp_trampoline
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#define setfunc_trampoline mips1_setfunc_trampoline
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#elif !defined(MIPS1) && defined(MIPS3) && !defined(MIPS32) && !defined(MIPS64) && !defined(MIPS3_5900)
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#define MachSetPID mips3_SetPID
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#define MIPS_TBIAP() mips3_TBIAP(mips_num_tlb_entries)
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#define MIPS_TBIS mips3_TBIS
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#define MachTLBUpdate mips3_TLBUpdate
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#define MachTLBWriteIndexedVPS mips3_TLBWriteIndexedVPS
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#define lwp_trampoline mips3_lwp_trampoline
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#define setfunc_trampoline mips3_setfunc_trampoline
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#define wbflush() mips3_wbflush()
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#elif !defined(MIPS1) && !defined(MIPS3) && defined(MIPS32) && !defined(MIPS64)
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#define MachSetPID mips32_SetPID
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#define MIPS_TBIAP() mips32_TBIAP(mips_num_tlb_entries)
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#define MIPS_TBIS mips32_TBIS
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#define MachTLBUpdate mips32_TLBUpdate
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#define MachTLBWriteIndexedVPS mips32_TLBWriteIndexedVPS
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#define lwp_trampoline mips32_lwp_trampoline
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#define setfunc_trampoline mips32_setfunc_trampoline
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#define wbflush() mips32_wbflush()
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#elif !defined(MIPS1) && !defined(MIPS3) && !defined(MIPS32) && defined(MIPS64)
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/* all common with mips3 */
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#define MachSetPID mips64_SetPID
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#define MIPS_TBIAP() mips64_TBIAP(mips_num_tlb_entries)
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#define MIPS_TBIS mips64_TBIS
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#define MachTLBUpdate mips64_TLBUpdate
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#define MachTLBWriteIndexedVPS mips64_TLBWriteIndexedVPS
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#define lwp_trampoline mips64_lwp_trampoline
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#define setfunc_trampoline mips64_setfunc_trampoline
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#define wbflush() mips64_wbflush()
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#elif !defined(MIPS1) && defined(MIPS3) && !defined(MIPS32) && !defined(MIPS64) && defined(MIPS3_5900)
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#define MachSetPID mips5900_SetPID
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#define MIPS_TBIAP() mips5900_TBIAP(mips_num_tlb_entries)
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#define MIPS_TBIS mips5900_TBIS
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#define MachTLBUpdate mips5900_TLBUpdate
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#define MachTLBWriteIndexedVPS mips5900_TLBWriteIndexedVPS
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#define lwp_trampoline mips5900_lwp_trampoline
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#define setfunc_trampoline mips5900_setfunc_trampoline
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#define wbflush() mips5900_wbflush()
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#else
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#define MachSetPID (*(mips_locore_jumpvec.setTLBpid))
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#define MIPS_TBIAP() (*(mips_locore_jumpvec.TBIAP))(mips_num_tlb_entries)
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#define MIPS_TBIS (*(mips_locore_jumpvec.TBIS))
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#define MachTLBUpdate (*(mips_locore_jumpvec.tlbUpdate))
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#define wbflush() (*(mips_locore_jumpvec.wbflush))()
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#define lwp_trampoline mips_locoresw.lsw_lwp_trampoline
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#define setfunc_trampoline mips_locoresw.lsw_setfunc_trampoline
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#endif
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#define CPU_IDLE mips_locoresw.lsw_cpu_idle
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/* cpu_switch_resume is called inside locore.S */
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/*
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* CPU identification, from PRID register.
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*/
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typedef int mips_prid_t;
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#define MIPS_PRID_REV(x) (((x) >> 0) & 0x00ff)
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#define MIPS_PRID_IMPL(x) (((x) >> 8) & 0x00ff)
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/* pre-MIPS32/64 */
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#define MIPS_PRID_RSVD(x) (((x) >> 16) & 0xffff)
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#define MIPS_PRID_REV_MIN(x) ((MIPS_PRID_REV(x) >> 0) & 0x0f)
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#define MIPS_PRID_REV_MAJ(x) ((MIPS_PRID_REV(x) >> 4) & 0x0f)
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/* MIPS32/64 */
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#define MIPS_PRID_CID(x) (((x) >> 16) & 0x00ff) /* Company ID */
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#define MIPS_PRID_CID_PREHISTORIC 0x00 /* Not MIPS32/64 */
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#define MIPS_PRID_CID_MTI 0x01 /* MIPS Technologies, Inc. */
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#define MIPS_PRID_CID_BROADCOM 0x02 /* Broadcom */
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#define MIPS_PRID_CID_ALCHEMY 0x03 /* Alchemy Semiconductor */
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#define MIPS_PRID_CID_SIBYTE 0x04 /* SiByte */
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#define MIPS_PRID_CID_SANDCRAFT 0x05 /* SandCraft */
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#define MIPS_PRID_CID_PHILIPS 0x06 /* Philips */
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#define MIPS_PRID_CID_TOSHIBA 0x07 /* Toshiba */
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#define MIPS_PRID_CID_LSI 0x08 /* LSI */
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/* 0x09 unannounced */
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/* 0x0a unannounced */
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#define MIPS_PRID_CID_LEXRA 0x0b /* Lexra */
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#define MIPS_PRID_CID_RMI 0x0c /* RMI / NetLogic */
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#define MIPS_PRID_COPTS(x) (((x) >> 24) & 0x00ff) /* Company Options */
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#ifdef _KERNEL
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/*
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* Global variables used to communicate CPU type, and parameters
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* such as cache size, from locore to higher-level code (e.g., pmap).
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*/
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extern mips_prid_t cpu_id;
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extern mips_prid_t fpu_id;
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extern int mips_num_tlb_entries;
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void mips_pagecopy(void *dst, void *src);
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void mips_pagezero(void *dst);
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#ifdef __HAVE_MIPS_MACHDEP_CACHE_CONFIG
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void mips_machdep_cache_config(void);
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#endif
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/*
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* trapframe argument passed to trap()
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*/
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#define TF_AST 0
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#define TF_V0 1
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#define TF_V1 2
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#define TF_A0 3
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#define TF_A1 4
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#define TF_A2 5
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#define TF_A3 6
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#define TF_T0 7
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#define TF_T1 8
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#define TF_T2 9
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#define TF_T3 10
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#if defined(__mips_n32) || defined(__mips_n64)
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#define TF_A4 11
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#define TF_A5 12
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#define TF_A6 13
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#define TF_A7 14
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#else
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#define TF_T4 11
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#define TF_T5 12
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#define TF_T6 13
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#define TF_T7 14
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#endif /* __mips_n32 || __mips_n64 */
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#define TF_TA0 11
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#define TF_TA1 12
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#define TF_TA2 13
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#define TF_TA3 14
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#define TF_T8 15
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#define TF_T9 16
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#define TF_RA 17
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#define TF_SR 18
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#define TF_MULLO 19
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#define TF_MULHI 20
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#define TF_EPC 21 /* may be changed by trap() call */
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#define TF_NREGS 22
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struct trapframe {
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mips_reg_t tf_regs[TF_NREGS];
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uint32_t tf_ppl; /* previous priority level */
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mips_reg_t tf_pad; /* for 8 byte aligned */
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};
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|
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/*
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* Stack frame for kernel traps. four args passed in registers.
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|
* A trapframe is pointed to by the 5th arg, and a dummy sixth argument
|
|
* is used to avoid alignment problems
|
|
*/
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|
|
|
struct kernframe {
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|
#if defined(__mips_o32) || defined(__mips_o64)
|
|
register_t cf_args[4 + 1];
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|
#if defined(__mips_o32)
|
|
register_t cf_pad; /* (for 8 word alignment) */
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|
#endif
|
|
#endif
|
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#if defined(__mips_n32) || defined(__mips_n64)
|
|
register_t cf_pad[2]; /* for 16 byte alignment */
|
|
#endif
|
|
register_t cf_sp;
|
|
register_t cf_ra;
|
|
struct trapframe cf_frame;
|
|
};
|
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#endif /* _KERNEL */
|
|
#endif /* _MIPS_LOCORE_H */
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