246 lines
6.6 KiB
C
246 lines
6.6 KiB
C
/*
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* OMAP watchdog timers, common code
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*
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* Copyright (c) 2007 Microsoft
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Microsoft
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTERS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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#include <sys/param.h>
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#include <sys/callout.h>
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#include <sys/cdefs.h>
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#include <sys/device.h>
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#include <sys/kernel.h>
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#include <sys/systm.h>
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#include <sys/wdog.h>
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#include <machine/param.h>
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#include <sys/bus.h>
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#include <dev/sysmon/sysmonvar.h>
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#include <arm/omap/omap_wdtvar.h>
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#include <arm/omap/omap_wdtreg.h>
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struct omapwdt32k_softc *omapwdt32k_sc;
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int omapwdt_sysconfig;
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static void
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omapwdt32k_sync(void)
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{
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/* The WCLR, WCRR, WLDR, WTGR and WSPR registers are
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* synchronized to the 32kHz clock. Each has an
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* associated status bit that's set when there's
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* a pending write. This function will wait for
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* all of those status bits to become clear so
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* the caller can safely write to any of the registers.
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*/
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while (bus_space_read_4(omapwdt32k_sc->sc_iot, omapwdt32k_sc->sc_ioh,
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WWPS) &
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(W_PEND_WSPR | W_PEND_WTGR | W_PEND_WLDR | W_PEND_WCRR |
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W_PEND_WCLR))
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delay(10);
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}
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static void
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omapwdt32k_start(void)
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{
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omapwdt32k_sync();
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bus_space_write_4(omapwdt32k_sc->sc_iot, omapwdt32k_sc->sc_ioh, WSPR,
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WD_ENABLE_WORD1);
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omapwdt32k_sync();
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bus_space_write_4(omapwdt32k_sc->sc_iot, omapwdt32k_sc->sc_ioh, WSPR,
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WD_ENABLE_WORD2);
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}
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static void
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omapwdt32k_stop(void)
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{
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omapwdt32k_sync();
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bus_space_write_4(omapwdt32k_sc->sc_iot, omapwdt32k_sc->sc_ioh, WSPR,
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WD_DISABLE_WORD1);
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omapwdt32k_sync();
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bus_space_write_4(omapwdt32k_sc->sc_iot, omapwdt32k_sc->sc_ioh, WSPR,
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WD_DISABLE_WORD2);
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}
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static void
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omapwdt32k_do_set_timeout(void)
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{
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if (omapwdt32k_sc->sc_armed) {
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/*
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* The watchdog must be disabled before writing to
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* the WCRR, WCLR:PTV, or WLDR registers.
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*/
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omapwdt32k_stop();
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}
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/* Make sure WLDR, WCRR, and WCLR are ready to be written to.
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*/
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omapwdt32k_sync();
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/* Make sure that the prescaler is set.
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*/
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bus_space_write_4(omapwdt32k_sc->sc_iot, omapwdt32k_sc->sc_ioh, WCLR,
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(WCLR_PTV(PTV) | WCLR_PRE(PRE)));
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/* Write the new count value to the load and
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* counter registers.
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*/
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bus_space_write_4(omapwdt32k_sc->sc_iot, omapwdt32k_sc->sc_ioh, WLDR,
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omapwdt32k_sc->sc_smw.smw_period ?
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WATCHDOG_COUNT(omapwdt32k_sc->sc_smw.smw_period)
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: 0xffffffff);
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bus_space_write_4(omapwdt32k_sc->sc_iot, omapwdt32k_sc->sc_ioh, WCRR,
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omapwdt32k_sc->sc_smw.smw_period ?
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WATCHDOG_COUNT(omapwdt32k_sc->sc_smw.smw_period)
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: 0xffffffff);
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/* Wait for the pending writes to go through.
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*/
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omapwdt32k_sync();
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/* Resume the watchdog if we had stopped it.
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*/
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if (omapwdt32k_sc->sc_armed)
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omapwdt32k_start();
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}
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void
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omapwdt32k_set_timeout(unsigned int period)
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{
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int s = splhigh();
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if (period != omapwdt32k_sc->sc_smw.smw_period) {
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omapwdt32k_sc->sc_smw.smw_period = period;
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omapwdt32k_do_set_timeout();
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}
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splx(s);
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}
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int
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omapwdt32k_enable(int enable)
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{
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int s;
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int prev_state;
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/* Just return if ddb is entered before the watchdog driver starts. */
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if (omapwdt32k_sc == NULL)
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return (0);
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prev_state = omapwdt32k_sc->sc_armed;
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/* Normalize the int to a boolean so we can compare values directly.
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*/
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enable = !!enable;
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s = splhigh();
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if (enable != omapwdt32k_sc->sc_armed) {
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if (enable) {
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/* Make sure that the watchdog timeout is up to date.
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*/
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omapwdt32k_do_set_timeout();
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omapwdt32k_start();
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} else {
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omapwdt32k_stop();
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}
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omapwdt32k_sc->sc_armed = enable;
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}
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splx(s);
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return prev_state;
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}
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int
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omapwdt32k_setmode(struct sysmon_wdog *smw)
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{
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struct omapwdt32k_softc *sc = smw->smw_cookie;
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int error = 0;
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if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) {
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omapwdt32k_enable(0);
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} else {
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if (smw->smw_period == WDOG_PERIOD_DEFAULT)
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sc->sc_smw.smw_period = OMAPWDT32K_DEFAULT_PERIOD;
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else
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sc->sc_smw.smw_period = smw->smw_period;
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omapwdt32k_set_timeout(sc->sc_smw.smw_period);
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omapwdt32k_enable(1);
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if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_KTICKLE)
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omapwdt32k_tickle(smw);
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}
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return error;
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}
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int
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omapwdt32k_tickle(struct sysmon_wdog *smw)
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{
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int s = splhigh();
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/*
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* To reload the timer counter and reset the prescaler counter
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* values without reaching overflow, a reload command can be
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* executed by accessing the watchdog trigger register (WTGR)
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* using a specific reload sequence.
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*
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* The specific reload sequence is performed when the written
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* value on the watchdog trigger register (WTGR) is different
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* from its previous value. In this case, reload is executed in
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* the same way as overflow autoreload, without a reset pulse
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* generation. The timer is loaded with the watchdog load register
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* (WLDR) value and the prescaler counter is reset.
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*
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* Write a new value into WTGR to reload WCRR (counter register)
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* with the value in WLDR (load register), thereby resetting the
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* watchdog.
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*/
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omapwdt32k_sync();
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bus_space_write_4(omapwdt32k_sc->sc_iot, omapwdt32k_sc->sc_ioh, WTGR,
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~bus_space_read_4(omapwdt32k_sc->sc_iot,
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omapwdt32k_sc->sc_ioh, WTGR));
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splx(s);
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return 0;
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}
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void
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omapwdt32k_reboot(void)
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{
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if (omapwdt32k_sc == NULL)
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return;
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const int s = splhigh();
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omapwdt32k_set_timeout(0);
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omapwdt32k_start();
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delay(100);
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splx(s);
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}
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