457 lines
13 KiB
C
457 lines
13 KiB
C
/* $NetBSD: clock.c,v 1.39 2010/12/20 00:25:45 matt Exp $ */
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/*
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* Copyright (c) 1982, 1990, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* the Systems Programming Group of the University of Utah Computer
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* Science Department.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: Utah Hdr: clock.c 1.18 91/01/21$
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* from: @(#)clock.c 8.2 (Berkeley) 1/12/94
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*/
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/*
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* Copyright (c) 1994 Gordon W. Ross
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* Copyright (c) 1993 Adam Glass
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* Copyright (c) 1988 University of Utah.
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*
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* This code is derived from software contributed to Berkeley by
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* the Systems Programming Group of the University of Utah Computer
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* Science Department.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: Utah Hdr: clock.c 1.18 91/01/21$
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* from: @(#)clock.c 8.2 (Berkeley) 1/12/94
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*/
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/*
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* Machine-dependent clock routines. Sun3X machines may have
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* either the Mostek 48T02 or the Intersil 7170 clock.
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*
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* It is tricky to determine which you have, because there is
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* always something responding at the address where the Mostek
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* clock might be found: either a Mostek or plain-old EEPROM.
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* Therefore, we cheat. If we find an Intersil clock, assume
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* that what responds at the end of the EEPROM space is just
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* plain-old EEPROM (not a Mostek clock). Worse, there are
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* H/W problems with probing for an Intersil on the 3/80, so
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* on that machine we "know" there is a Mostek clock.
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*
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* Note that the probing algorithm described above requires
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* that we probe the intersil before we probe the mostek!
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: clock.c,v 1.39 2010/12/20 00:25:45 matt Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/time.h>
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#include <sys/kernel.h>
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#include <sys/device.h>
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#include <uvm/uvm_extern.h>
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#include <m68k/asm_single.h>
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#include <machine/autoconf.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <machine/idprom.h>
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#include <machine/leds.h>
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#include <dev/clock_subr.h>
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#include <dev/ic/intersil7170reg.h>
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#include <dev/ic/intersil7170var.h>
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#include <dev/ic/mk48txxreg.h>
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#include <dev/ic/mk48txxvar.h>
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#include <sun3/sun3/machdep.h>
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#include <sun3/sun3/interreg.h>
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extern int intrcnt[];
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#define SUN3_470 Yes
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#define CLOCK_PRI 5
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#define IREG_CLK_BITS (IREG_CLOCK_ENAB_7 | IREG_CLOCK_ENAB_5)
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#define MKCLOCK_REG_OFFSET (MK48T02_CLKOFF + MK48TXX_ICSR)
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/*
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* Only one of these two variables should be non-zero after
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* autoconfiguration determines which clock we have.
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*/
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static volatile void *intersil_va;
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static volatile void *mostek_clk_va;
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void _isr_clock(void); /* in locore.s */
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void clock_intr(struct clockframe);
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static int clock_match(device_t, cfdata_t, void *);
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static void clock_attach(device_t, device_t, void *);
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CFATTACH_DECL_NEW(clock, sizeof(struct mk48txx_softc),
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clock_match, clock_attach, NULL, NULL);
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#ifdef SUN3_470
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#define intersil_clock ((volatile struct intersil7170 *)intersil_va)
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#define intersil_clear() (void)intersil_clock->clk_intr_reg
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static int oclock_match(device_t, cfdata_t, void *);
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static void oclock_attach(device_t, device_t, void *);
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CFATTACH_DECL_NEW(oclock, sizeof(struct intersil7170_softc),
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oclock_match, oclock_attach, NULL, NULL);
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/*
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* Is there an intersil clock?
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*/
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static int
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oclock_match(device_t parent, cfdata_t cf, void *aux)
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{
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struct confargs *ca = aux;
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/* This driver only supports one unit. */
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if (intersil_va)
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return 0;
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/*
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* The 3/80 can not probe the Intersil absent,
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* but it never has one, so "just say no."
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*/
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if (cpu_machine_id == ID_SUN3X_80)
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return 0;
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/* OK, really probe for the Intersil. */
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if (bus_peek(ca->ca_bustype, ca->ca_paddr, 1) == -1)
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return 0;
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/* Default interrupt priority. */
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if (ca->ca_intpri == -1)
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ca->ca_intpri = CLOCK_PRI;
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return 1;
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}
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/*
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* Attach the intersil clock.
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*/
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static void
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oclock_attach(device_t parent, device_t self, void *aux)
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{
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struct intersil7170_softc *sc = device_private(self);
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struct confargs *ca = aux;
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sc->sc_dev = self;
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/* Get a mapping for it. */
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sc->sc_bst = ca->ca_bustag;
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if (bus_space_map(sc->sc_bst, ca->ca_paddr, sizeof(struct intersil7170),
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0, &sc->sc_bsh) != 0) {
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aprint_error(": can't map registers\n");
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return;
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}
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intersil_va = bus_space_vaddr(sc->sc_bst, sc->sc_bsh);
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#ifdef DIAGNOSTIC
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/* Verify correct probe order... */
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if (mostek_clk_va) {
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mostek_clk_va = NULL;
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aprint_normal("\n");
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aprint_error_dev(self, "warning - mostek found also!\n");
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}
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#endif
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/*
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* Set the clock to the correct interrupt rate, but
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* do not enable the interrupt until cpu_initclocks.
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* XXX: Actually, the interrupt_reg should be zero
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* at this point, so the clock interrupts should not
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* affect us, but we need to set the rate...
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*/
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bus_space_write_1(sc->sc_bst, sc->sc_bsh, INTERSIL_ICMD,
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INTERSIL_COMMAND(INTERSIL_CMD_RUN, INTERSIL_CMD_IDISABLE));
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(void)bus_space_read_1(sc->sc_bst, sc->sc_bsh, INTERSIL_IINTR);
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/* Set the clock to 100 Hz, but do not enable it yet. */
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bus_space_write_1(sc->sc_bst, sc->sc_bsh,
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INTERSIL_IINTR, INTERSIL_INTER_CSECONDS);
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sc->sc_year0 = 1968;
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intersil7170_attach(sc);
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aprint_normal("\n");
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/*
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* Can not hook up the ISR until cpu_initclocks()
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* because hardclock is not ready until then.
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* For now, the handler is _isr_autovec(), which
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* will complain if it gets clock interrupts.
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*/
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}
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#endif /* SUN3_470 */
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/*
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* Is there a Mostek clock? Hard to tell...
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* (See comment at top of this file.)
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*/
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static int
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clock_match(device_t parent, cfdata_t cf, void *args)
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{
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struct confargs *ca = args;
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/* This driver only supports one unit. */
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if (mostek_clk_va)
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return 0;
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/* If intersil was found, use that. */
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if (intersil_va)
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return 0;
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/* Else assume a Mostek is there... */
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/* Default interrupt priority. */
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if (ca->ca_intpri == -1)
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ca->ca_intpri = CLOCK_PRI;
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return 1;
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}
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/*
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* Attach the mostek clock.
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*/
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static void
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clock_attach(device_t parent, device_t self, void *aux)
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{
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struct mk48txx_softc *sc = device_private(self);
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struct confargs *ca = aux;
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sc->sc_dev = self;
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sc->sc_bst = ca->ca_bustag;
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if (bus_space_map(sc->sc_bst, ca->ca_paddr - MKCLOCK_REG_OFFSET,
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MK48T02_CLKSZ, 0, &sc->sc_bsh) != 0) {
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aprint_error(": can't map device space\n");
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return;
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}
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mostek_clk_va = bus_space_vaddr(sc->sc_bst, sc->sc_bsh);
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sc->sc_model = "mk48t02";
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sc->sc_year0 = 1968;
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mk48txx_attach(sc);
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aprint_normal("\n");
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}
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/*
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* Set and/or clear the desired clock bits in the interrupt
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* register. We have to be extremely careful that we do it
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* in such a manner that we don't get ourselves lost.
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* XXX: Watch out! It's really easy to break this!
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*/
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void
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set_clk_mode(u_char on, u_char off, int enable_clk)
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{
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u_char interreg;
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/*
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* If we have not yet mapped the register,
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* then we do not want to do any of this...
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*/
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if (!interrupt_reg)
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return;
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#ifdef DIAGNOSTIC
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/* Assertion: were are at splhigh! */
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if ((getsr() & PSL_IPL) < PSL_IPL7)
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panic("set_clk_mode: bad ipl");
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#endif
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/*
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* make sure that we are only playing w/
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* clock interrupt register bits
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*/
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on &= IREG_CLK_BITS;
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off &= IREG_CLK_BITS;
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/* First, turn off the "master" enable bit. */
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single_inst_bclr_b(*interrupt_reg, IREG_ALL_ENAB);
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/*
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* Save the current interrupt register clock bits,
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* and turn off/on the requested bits in the copy.
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*/
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interreg = *interrupt_reg & IREG_CLK_BITS;
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interreg &= ~off;
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interreg |= on;
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/* Clear the CLK5 and CLK7 bits to clear the flip-flops. */
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single_inst_bclr_b(*interrupt_reg, IREG_CLK_BITS);
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#ifdef SUN3_470
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if (intersil_va) {
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/*
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* Then disable clock interrupts, and read the clock's
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* interrupt register to clear any pending signals there.
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*/
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intersil_clock->clk_cmd_reg =
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INTERSIL_COMMAND(INTERSIL_CMD_RUN, INTERSIL_CMD_IDISABLE);
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intersil_clear();
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}
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#endif /* SUN3_470 */
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/* Set the requested bits in the interrupt register. */
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single_inst_bset_b(*interrupt_reg, interreg);
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#ifdef SUN3_470
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/* Turn the clock back on (maybe) */
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if (intersil_va && enable_clk)
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intersil_clock->clk_cmd_reg =
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INTERSIL_COMMAND(INTERSIL_CMD_RUN, INTERSIL_CMD_IENABLE);
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#endif /* SUN3_470 */
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/* Finally, turn the "master" enable back on. */
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single_inst_bset_b(*interrupt_reg, IREG_ALL_ENAB);
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}
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/*
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* Set up the real-time clock (enable clock interrupts).
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* Leave stathz 0 since there is no secondary clock available.
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* Note that clock interrupts MUST STAY DISABLED until here.
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*/
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void
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cpu_initclocks(void)
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{
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int s;
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s = splhigh();
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/* Install isr (in locore.s) that calls clock_intr(). */
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isr_add_custom(CLOCK_PRI, (void *)_isr_clock);
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/* Now enable the clock at level 5 in the interrupt reg. */
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set_clk_mode(IREG_CLOCK_ENAB_5, 0, 1);
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splx(s);
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}
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/*
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* This doesn't need to do anything, as we have only one timer and
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* profhz==stathz==hz.
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*/
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void
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setstatclockrate(int newhz)
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{
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/* nothing */
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}
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/*
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* Clock interrupt handler (for both Intersil and Mostek).
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* XXX - Is it worth the trouble to save a few cycles here
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* by making two separate interrupt handlers?
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*
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* This is called by the "custom" interrupt handler.
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* Note that we can get ZS interrupts while this runs,
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* and zshard may touch the interrupt_reg, so we must
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* be careful to use the single_inst_* macros to modify
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* the interrupt register atomically.
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*/
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void
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clock_intr(struct clockframe cf)
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{
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extern char _Idle[]; /* locore.s */
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idepth++;
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#ifdef SUN3_470
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if (intersil_va) {
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/* Read the clock interrupt register. */
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intersil_clear();
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}
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#endif /* SUN3_470 */
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/* Pulse the clock intr. enable low. */
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single_inst_bclr_b(*interrupt_reg, IREG_CLOCK_ENAB_5);
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single_inst_bset_b(*interrupt_reg, IREG_CLOCK_ENAB_5);
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#ifdef SUN3_470
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if (intersil_va) {
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/* Read the clock intr. reg. AGAIN! */
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intersil_clear();
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}
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#endif /* SUN3_470 */
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intrcnt[CLOCK_PRI]++;
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curcpu()->ci_data.cpu_nintr++;
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/* Entertainment! */
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if (cf.cf_pc == (long)_Idle)
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leds_intr();
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/* Call common clock interrupt handler. */
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hardclock(&cf);
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idepth--;
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}
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