matt ee6cde04ff Don't use an asm in pmap_activate to update the TTBR, use cpu_setttb instead ... but add a second argument to it to indicate whether the TLB/caches need to be flushed. Default cortex to pmap_needs_fixup = 1. But check the MMFR3 field to see if the fixed can be skipped. Use a cf_flag bit 0 to indicate whether the A9 L2 cache should disable (bit 0 = 1) or enabeld (bit = 0). With these changes, the A9 MMU can use traverse caches to do MMU tablewalks Also, make sure all memory has the shareable bit for the A9.		2012-09-22 00:33:36 +00:00
..
com_obio.c	#include <sys/bus.h> instead of <machine/bus.h>.	2011-07-01 20:36:42 +00:00
npwr_fc_machdep.c	Don't use an asm in pmap_activate to update the TTBR, use cpu_setttb instead	2012-09-22 00:33:36 +00:00
npwr_fc_pci.c	#include <sys/bus.h> instead of <machine/bus.h>.	2011-07-01 20:36:42 +00:00