194 lines
5.4 KiB
C
194 lines
5.4 KiB
C
/* $NetBSD: gemini_gmacvar.h,v 1.3 2008/12/23 02:15:10 matt Exp $ */
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/*-
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* Copyright (c) 2008 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Matt Thomas <matt@3am-software.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ARM_GEMINI_GEMINI_GMACVAR_H
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#define _ARM_GEMINI_GEMINI_GMACVAR_H
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#include <sys/device.h>
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#include <sys/queue.h>
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#include <net/if.h>
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#include <net/if_media.h>
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#include <dev/mii/mii.h>
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#include <dev/mii/miivar.h>
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#include <arm/gemini/gemini_gmacreg.h>
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typedef struct gmac_hwqueue gmac_hwqueue_t;
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typedef struct gmac_hwqmem gmac_hwqmem_t;
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typedef struct gmac_mapcache gmac_mapcache_t;
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#define MAX_TXMAPS 256
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#define MIN_TXMAPS 16
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#define MAX_RXMAPS 128
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#define MIN_RXMAPS 8
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#define RXQ_NDESCS 256
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#define TXQ_NDESCS 128
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struct gmac_mapcache {
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bus_dma_tag_t mc_dmat;
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bus_size_t mc_mapsize;
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size_t mc_nsegs;
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size_t mc_free;
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size_t mc_used;
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size_t mc_max;
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bus_dmamap_t mc_maps[0];
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};
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struct gmac_softc {
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device_t sc_dev;
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bus_space_tag_t sc_iot;
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bus_space_handle_t sc_ioh;
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bus_dma_tag_t sc_dmat;
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/*
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* MDIO state
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*/
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kmutex_t sc_mdiolock;
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uint32_t sc_mdiobits;
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device_t sc_gpio_dev;
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uint8_t sc_gpio_mdclk;
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uint8_t sc_gpio_mdin;
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uint8_t sc_gpio_mdout;
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/*
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* What GMAC ports have attached?
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*/
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uint8_t sc_ports;
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uint8_t sc_running;
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/*
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* The hardware free queue and software free queue are shared
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* resources. As are the dmamap caches.
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*/
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gmac_hwqueue_t *sc_swfreeq;
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gmac_hwqueue_t *sc_hwfreeq;
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gmac_mapcache_t *sc_rxmaps;
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gmac_mapcache_t *sc_txmaps;
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size_t sc_swfree_min; /* min mbufs to keep on swfreeq */
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size_t sc_rxpkts_per_sec;
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/*
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* What interrupts are enabled for both ports?
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*/
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uint32_t sc_int_enabled[5];
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uint32_t sc_int_select[5];
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};
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struct gmac_attach_args {
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bus_space_tag_t gma_iot;
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bus_space_handle_t gma_ioh;
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bus_dma_tag_t gma_dmat;
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int gma_port;
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int gma_phy;
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int gma_intr;
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mii_readreg_t gma_mii_readreg;
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mii_writereg_t gma_mii_writereg;
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};
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struct gmac_hwqmem {
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bus_dma_tag_t hqm_dmat;
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bus_dmamap_t hqm_dmamap;
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gmac_mapcache_t *hqm_mc;
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gmac_desc_t *hqm_base;
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bus_size_t hqm_memsize;
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bus_dma_segment_t hqm_segs[1];
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size_t hqm_ndesc;
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size_t hqm_nqueue;
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int hqm_nsegs;
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uint8_t hqm_refs;
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uint8_t hqm_flags;
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#define HQM_TX 0x0001
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#define HQM_RX 0x0000
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#define HQM_PRODUCER 0x0002
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#define HQM_CONSUMER 0x0000
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};
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struct gmac_hwqueue {
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gmac_desc_t *hwq_base;
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gmac_hwqmem_t *hwq_hqm;
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union {
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SLIST_ENTRY(gmac_hwqueue) qun_link;
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SLIST_HEAD(,gmac_hwqueue) qun_producers;
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struct gmac_hwqueue *qun_producer;
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} hwq_qun;
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#define hwq_link hwq_qun.qun_link
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#define hwq_producers hwq_qun.qun_producers
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#define hwq_producer hwq_qun.qun_producer
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struct ifnet *hwq_ifp;
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struct ifqueue hwq_ifq;
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struct mbuf *hwq_rxmbuf;
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struct mbuf **hwq_mp;
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bus_space_tag_t hwq_iot;
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bus_space_handle_t hwq_qrwptr_ioh;
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/*
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* These are in units of gmac_desc_t, not bytes.
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*/
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size_t hwq_qoff; /* offset in descriptors to start */
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uint16_t hwq_wptr; /* next descriptor to write */
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uint16_t hwq_rptr; /* next descriptor to read */
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uint16_t hwq_free; /* descriptors can be produced */
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uint16_t hwq_size; /* total number of descriptors */
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uint8_t hwq_ref;
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};
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#ifdef _KERNEL
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gmac_hwqmem_t *
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gmac_hwqmem_create(gmac_mapcache_t *, size_t, size_t, int);
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void gmac_hwqmem_destroy(gmac_hwqmem_t *);
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void gmac_hwqueue_destroy(gmac_hwqueue_t *);
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gmac_hwqueue_t *
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gmac_hwqueue_create(gmac_hwqmem_t *, bus_space_tag_t,
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bus_space_handle_t, bus_size_t, bus_size_t, size_t);
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gmac_desc_t *
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gmac_hwqueue_desc(gmac_hwqueue_t *, size_t);
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void gmac_hwqueue_sync(gmac_hwqueue_t *);
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size_t gmac_hwqueue_consume(gmac_hwqueue_t *, size_t);
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void gmac_hwqueue_produce(gmac_hwqueue_t *, size_t);
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gmac_mapcache_t *
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gmac_mapcache_create(bus_dma_tag_t, size_t, bus_size_t, int);
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void gmac_mapcache_destroy(gmac_mapcache_t **);
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int gmac_mapcache_fill(gmac_mapcache_t *, size_t);
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bus_dmamap_t
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gmac_mapcache_get(gmac_mapcache_t *);
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void gmac_mapcache_put(gmac_mapcache_t *, bus_dmamap_t);
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size_t gmac_rxproduce(gmac_hwqueue_t *, size_t);
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void gmac_swfree_min_update(struct gmac_softc *);
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void gmac_intr_update(struct gmac_softc *);
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#endif
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#endif /* _ARM_GEMINI_GEMINI_GMACVAR_H */
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