184 lines
5.7 KiB
C
184 lines
5.7 KiB
C
/* $NetBSD: ad1848reg.h,v 1.4 1997/05/07 20:23:53 augustss Exp $ */
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/*
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* Copyright (c) 1994 John Brezak
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* Copyright (c) 1991-1993 Regents of the University of California.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the Computer Systems
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* Engineering Group at Lawrence Berkeley Laboratory.
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* 4. Neither the name of the University nor of the Laboratory may be used
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* to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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/*
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* Copyright (c) 1993 Analog Devices Inc. All rights reserved
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*/
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/* parent driver is primarily responsible for checking this */
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#define AD1848_BASE_VALID(base) (((base) & 0x003) == 0)
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/* AD1848 direct registers */
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#define AD1848_IADDR 0x00
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#define AD1848_IDATA 0x01
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#define AD1848_STATUS 0x02
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#define AD1848_PIO 0x03
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/* Gain constants */
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#define GAIN_0 0x00
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#define GAIN_1_5 0x01
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#define GAIN_3 0x02
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#define GAIN_4_5 0x03
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#define GAIN_6 0x04
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#define GAIN_7_5 0x05
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#define GAIN_9 0x06
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#define GAIN_10_5 0x07
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#define GAIN_12 0x08
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#define GAIN_13_5 0x09
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#define GAIN_15 0x0a
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#define GAIN_16_5 0x0b
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#define GAIN_18 0x0c
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#define GAIN_19_5 0x0d
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#define GAIN_21 0x0e
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#define GAIN_22_5 0x0f
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/* Attenuation constants */
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#define ATTEN_0 0x00
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#define ATTEN_1_5 0x01
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#define ATTEN_3 0x02
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#define ATTEN_4_5 0x03
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#define ATTEN_6 0x04
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#define ATTEN_7_5 0x05
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#define ATTEN_9 0x06
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#define ATTEN_10_5 0x07
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#define ATTEN_12 0x08
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#define ATTEN_13_5 0x09
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#define ATTEN_15 0x0a
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#define ATTEN_16_5 0x0b
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#define ATTEN_18 0x0c
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#define ATTEN_19_5 0x0d
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#define ATTEN_21 0x0e
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#define ATTEN_22_5 0x0f
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/* AD1848 Sound Port bit defines */
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#define SP_IN_INIT 0x80
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#define MODE_CHANGE_ENABLE 0x40
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#define TRANSFER_DISABLE 0x20
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#define ADDRESS_MASK 0xe0
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/* Status bits */
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#define INTERRUPT_STATUS 0x01
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#define PLAYBACK_READY 0x02
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#define PLAYBACK_LEFT 0x04
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/* pbright is not left */
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#define PLAYBACK_UPPER 0x08
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/* bplower is not upper */
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#define SAMPLE_ERROR 0x10
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#define CAPTURE_READY 0x20
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#define CAPTURE_LEFT 0x40
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/* cpright is not left */
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#define CAPTURE_UPPER 0x80
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/* cplower is not upper */
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/* Input & Output regs bits */
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#define LINE_INPUT 0x00
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#define AUX_INPUT 0x40
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#define MIC_INPUT 0x80
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#define MIXED_DAC_INPUT 0xc0
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#define INPUT_GAIN_MASK 0xf0
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#define INPUT_MIC_GAIN_ENABLE 0x20
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#define INPUT_SOURCE_MASK 0x3f
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#define AUX_INPUT_ATTEN_BITS 0x1f
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#define AUX_INPUT_ATTEN_MASK 0xe0
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#define AUX_INPUT_MUTE 0x80
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#define OUTPUT_MUTE 0x80
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#define OUTPUT_ATTEN_BITS 0x3f
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#define OUTPUT_ATTEN_MASK 0xc0
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/* Clock and Data format reg bits (some also Capture Data format) */
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#define CLOCK_XTAL2 0x01
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#define CLOCK_XTAL1 0x00
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#define CLOCK_FREQ_MASK 0xf1
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#define FMT_MONO 0x00
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#define FMT_STEREO 0x10
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#define FORMAT_MASK 0x1f
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#define FMT_PCM8 0x00 /* 8-bit unsigned */
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#define FMT_ULAW 0x20 /* 8-bit mu-law */
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#define FMT_TWOS_COMP 0x40 /* 16-bit signed */
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#define FMT_ALAW 0x60 /* 8-bit alaw */
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#define FMT_ADPCM 0xa0 /* IMA ADPCM */
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#define FMT_TWOS_COMP_BE 0xc0 /* 16-bit signed, big endian */
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/* Interface Configuration reg bits */
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#define PLAYBACK_ENABLE 0x01
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#define CAPTURE_ENABLE 0x02
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#define DUAL_DMA 0x00
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#define SINGLE_DMA 0x04
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#define AUTO_CAL_ENABLE 0x08
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#define PLAYBACK_PIO_ENABLE 0x40
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#define CAPTURE_PIO_ENABLE 0x80
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/* Pin control bits */
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#define INTERRUPT_ENABLE 0x02
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#define XCTL0_ENABLE 0x40
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#define XCTL1_ENABLE 0x80
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/* Test and init reg bits */
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#define OVERRANGE_LEFT_MASK 0xfc
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#define OVERRANGE_RIGHT_MASK 0xf3
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#define DATA_REQUEST_STATUS 0x10
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#define AUTO_CAL_IN_PROG 0x20
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#define PLAYBACK_UNDERRUN 0x40
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#define CAPTURE_OVERRUN 0x80
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/* Miscellaneous Control reg bits */
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#define ID_MASK 0x70
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#define MODE2 0x40
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/* Digital Mix Control reg bits */
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#define DIGITAL_MIX1_ENABLE 0x01
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#define MIX_ATTEN_MASK 0xfc
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/* AD1848 Sound Port reg defines */
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#define SP_LEFT_INPUT_CONTROL 0x00
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#define SP_RIGHT_INPUT_CONTROL 0x01
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#define SP_LEFT_AUX1_CONTROL 0x02
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#define SP_RIGHT_AUX1_CONTROL 0x03
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#define SP_LEFT_AUX2_CONTROL 0x04
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#define SP_RIGHT_AUX2_CONTROL 0x05
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#define SP_LEFT_OUTPUT_CONTROL 0x06
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#define SP_RIGHT_OUTPUT_CONTROL 0x07
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#define SP_CLOCK_DATA_FORMAT 0x08
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#define SP_INTERFACE_CONFIG 0x09
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#define SP_PIN_CONTROL 0x0A
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#define SP_TEST_AND_INIT 0x0B
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#define SP_MISC_INFO 0x0C
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#define SP_DIGITAL_MIX 0x0D
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#define SP_UPPER_BASE_COUNT 0x0E
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#define SP_LOWER_BASE_COUNT 0x0F
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