77b78cdcff
- new code for Samsung S3C2440 SoC. - update for other S3C2xx0. This port was done by Paul Fleischer.
63 lines
2.5 KiB
C
63 lines
2.5 KiB
C
/* $NetBSD: s3c24x0_spi.h,v 1.3 2012/01/30 03:28:33 nisimura Exp $ */
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/*
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* Copyright (c) 2004 Genetec corporation. All rights reserved.
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* Written by Hiroyuki Bessho for Genetec corporation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of Genetec corporation may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY GENETEC CORP. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORP.
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _S3C2410_SPI_H_
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#define _S3C2410_SPI_H_
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#include <arm/s3c2xx0/s3c24x0var.h>
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struct ssspi_softc;
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/*
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* attach arguments for sub-devices hooked to SPI ports.
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*/
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struct ssspi_attach_args {
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s3c2xx0_chipset_tag_t spia_sc;
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bus_space_tag_t spia_iot;
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bus_space_handle_t spia_ioh; /* SPI controller registers */
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bus_space_handle_t spia_gpioh; /* GPIO registers. SPI devices often
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needs additional pins */
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bus_dma_tag_t spia_dmat;
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short spia_intr; /* interrupt from SPI */
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short spia_index; /* index number of SPI unit (0|1) */
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short spia_aux_intr; /* additional interrupt */
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};
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int s3c24x0_spi_setup(struct ssspi_softc *, uint32_t, int, int);
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int s3c24x0_spi_master_send(struct ssspi_softc *, uint8_t);
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int s3c24x0_spi_wait(struct ssspi_softc *, uint8_t*);
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void s3c24x0_spi_spin_wait(struct ssspi_softc *sc);
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int s3c24x0_spi_bps(struct ssspi_softc *sc, int bps);
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#endif /* _S3C2410_SPI_H_ */
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