a7d44c2503
Change the bus_dmamap_sync() macro to test the ops argument against pre- and post- constants. The compiler will optimize out dead code because of the constants. Since post- operations are not needed on ARM (except for ISA bounce buffers), this eliminate a large number of function calls which are noops, each of which cost at least 6 cycles just in the call and return overhead (not to mention whatever other useless work the compiler decides to do in the callee).
345 lines
10 KiB
C
345 lines
10 KiB
C
/* $NetBSD: i80321.c,v 1.7 2002/08/17 20:46:28 thorpej Exp $ */
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/*
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* Copyright (c) 2002 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Jason R. Thorpe for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Autoconfiguration support for the Intel i80321 I/O Processor.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#define _ARM32_BUS_DMA_PRIVATE
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#include <machine/bus.h>
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#include <arm/xscale/i80321reg.h>
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#include <arm/xscale/i80321var.h>
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/*
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* Statically-allocated bus_space stucture used to access the
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* i80321's own registers.
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*/
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struct bus_space i80321_bs_tag;
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/*
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* There can be only one i80321, so we keep a global pointer to
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* the softc, so board-specific code can use features of the
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* i80321 without having to have a handle on the softc itself.
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*/
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struct i80321_softc *i80321_softc;
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static int i80321_iopxs_print(void *, const char *);
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static int i80321_pcibus_print(void *, const char *);
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/* Built-in devices. */
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static const struct iopxs_device {
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const char *id_name;
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bus_addr_t id_offset;
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bus_size_t id_size;
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} iopxs_devices[] = {
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{ "iopaau", VERDE_AAU_BASE, VERDE_AAU_SIZE },
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{ "iopdma", VERDE_DMA_BASE, VERDE_DMA_SIZE },
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{ "iopssp", VERDE_SSP_BASE, VERDE_SSP_SIZE },
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{ "iopwdog", 0, 0 },
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{ NULL, 0, 0 }
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};
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static void i80321_pci_dma_init(struct i80321_softc *);
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static void i80321_local_dma_init(struct i80321_softc *);
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/*
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* i80321_attach:
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*
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* Board-independent attach routine for the i80321.
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*/
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void
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i80321_attach(struct i80321_softc *sc)
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{
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struct pcibus_attach_args pba;
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const struct iopxs_device *id;
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struct iopxs_attach_args ia;
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pcireg_t preg;
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i80321_softc = sc;
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/*
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* Slice off some useful subregion handles.
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*/
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if (bus_space_subregion(sc->sc_st, sc->sc_sh, VERDE_ATU_BASE,
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VERDE_ATU_SIZE, &sc->sc_atu_sh))
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panic("%s: unable to subregion ATU registers\n",
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sc->sc_dev.dv_xname);
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/* We expect the Memory Controller to be already sliced off. */
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/*
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* Program the Inbound windows.
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*/
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if (sc->sc_is_host) {
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
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PCI_MAPREG_START, sc->sc_iwin[0].iwin_base_lo);
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
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PCI_MAPREG_START + 0x04, sc->sc_iwin[0].iwin_base_hi);
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}
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IALR0,
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(0xffffffff - (sc->sc_iwin[0].iwin_size - 1)) & 0xffffffc0);
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IATVR0,
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sc->sc_iwin[0].iwin_xlate);
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if (sc->sc_is_host) {
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
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PCI_MAPREG_START + 0x08, sc->sc_iwin[1].iwin_base_lo);
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
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PCI_MAPREG_START + 0x0c, sc->sc_iwin[1].iwin_base_hi);
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}
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IALR1,
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(0xffffffff - (sc->sc_iwin[1].iwin_size - 1)) & 0xffffffc0);
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/* no xlate for window 1 */
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if (sc->sc_is_host) {
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
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PCI_MAPREG_START + 0x10, sc->sc_iwin[2].iwin_base_lo);
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
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PCI_MAPREG_START + 0x14, sc->sc_iwin[2].iwin_base_hi);
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}
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IALR2,
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(0xffffffff - (sc->sc_iwin[2].iwin_size - 1)) & 0xffffffc0);
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IATVR2,
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sc->sc_iwin[2].iwin_xlate);
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if (sc->sc_is_host) {
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
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ATU_IABAR3, sc->sc_iwin[3].iwin_base_lo);
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
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ATU_IAUBAR3, sc->sc_iwin[3].iwin_base_hi);
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}
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IALR3,
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(0xffffffff - (sc->sc_iwin[3].iwin_size - 1)) & 0xffffffc0);
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IATVR3,
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sc->sc_iwin[3].iwin_xlate);
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/*
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* Mask (disable) the ATU interrupt sources.
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* XXX May want to revisit this if we encounter
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* XXX an application that wants it.
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*/
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
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ATU_ATUIMR,
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ATUIMR_IMW1BU|ATUIMR_ISCEM|ATUIMR_RSCEM|ATUIMR_PST|
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ATUIMR_DPE|ATUIMR_P_SERR_ASRT|ATUIMR_PMA|ATUIMR_PTAM|
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ATUIMR_PTAT|ATUIMR_PMPE);
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/*
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* Program the outbound windows.
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*/
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
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ATU_OIOWTVR, sc->sc_ioout_xlate);
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
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ATU_OMWTVR0, sc->sc_owin[0].owin_xlate_lo);
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
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ATU_OUMWTVR0, sc->sc_owin[0].owin_xlate_hi);
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
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ATU_OMWTVR1, sc->sc_owin[1].owin_xlate_lo);
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
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ATU_OUMWTVR1, sc->sc_owin[1].owin_xlate_hi);
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/*
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* Set up the ATU configuration register. All we do
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* right now is enable Outbound Windows.
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*/
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_ATUCR,
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ATUCR_OUT_EN);
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/*
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* Enable bus mastering, memory access, SERR, and parity
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* checking on the ATU.
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*/
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if (sc->sc_is_host) {
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preg = bus_space_read_4(sc->sc_st, sc->sc_atu_sh,
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PCI_COMMAND_STATUS_REG);
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preg |= PCI_COMMAND_MEM_ENABLE | PCI_COMMAND_MASTER_ENABLE |
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PCI_COMMAND_PARITY_ENABLE | PCI_COMMAND_SERR_ENABLE;
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bus_space_write_4(sc->sc_st, sc->sc_atu_sh,
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PCI_COMMAND_STATUS_REG, preg);
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}
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/* Initialize the bus space tags. */
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i80321_io_bs_init(&sc->sc_pci_iot, sc);
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i80321_mem_bs_init(&sc->sc_pci_memt, sc);
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/* Initialize the PCI chipset tag. */
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i80321_pci_init(&sc->sc_pci_chipset, sc);
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/* Initialize the DMA tags. */
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i80321_pci_dma_init(sc);
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i80321_local_dma_init(sc);
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/*
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* Attach all the IOP built-ins.
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*/
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for (id = iopxs_devices; id->id_name != NULL; id++) {
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ia.ia_name = id->id_name;
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ia.ia_st = sc->sc_st;
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ia.ia_sh = sc->sc_sh;
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ia.ia_dmat = &sc->sc_local_dmat;
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ia.ia_offset = id->id_offset;
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ia.ia_size = id->id_size;
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(void) config_found(&sc->sc_dev, &ia, i80321_iopxs_print);
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}
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/*
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* Attach the PCI bus.
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*/
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preg = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCIXSR);
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preg = PCIXSR_BUSNO(preg);
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if (preg == 0xff)
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preg = 0;
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pba.pba_busname = "pci";
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pba.pba_iot = &sc->sc_pci_iot;
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pba.pba_memt = &sc->sc_pci_memt;
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pba.pba_dmat = &sc->sc_pci_dmat;
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pba.pba_pc = &sc->sc_pci_chipset;
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pba.pba_bus = preg;
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pba.pba_bridgetag = NULL;
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pba.pba_intrswiz = 0; /* XXX what if busno != 0? */
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pba.pba_intrtag = 0;
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pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED |
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PCI_FLAGS_MRL_OKAY | PCI_FLAGS_MRM_OKAY | PCI_FLAGS_MWI_OKAY;
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(void) config_found(&sc->sc_dev, &pba, i80321_pcibus_print);
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}
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/*
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* i80321_iopxs_print:
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*
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* Autoconfiguration cfprint routine when attaching
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* to the "iopxs" device.
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*/
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static int
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i80321_iopxs_print(void *aux, const char *pnp)
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{
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return (QUIET);
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}
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/*
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* i80321_pcibus_print:
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*
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* Autoconfiguration cfprint routine when attaching
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* to the "pcibus" attribute.
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*/
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static int
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i80321_pcibus_print(void *aux, const char *pnp)
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{
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struct pcibus_attach_args *pba = aux;
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if (pnp)
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printf("%s at %s", pba->pba_busname, pnp);
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printf(" bus %d", pba->pba_bus);
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return (UNCONF);
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}
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/*
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* i80321_pci_dma_init:
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*
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* Initialize the PCI DMA tag.
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*/
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static void
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i80321_pci_dma_init(struct i80321_softc *sc)
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{
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bus_dma_tag_t dmat = &sc->sc_pci_dmat;
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struct arm32_dma_range *dr = &sc->sc_pci_dma_range;
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dr->dr_sysbase = sc->sc_iwin[2].iwin_xlate;
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dr->dr_busbase = PCI_MAPREG_MEM_ADDR(sc->sc_iwin[2].iwin_base_lo);
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dr->dr_len = sc->sc_iwin[2].iwin_size;
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dmat->_ranges = dr;
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dmat->_nranges = 1;
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dmat->_dmamap_create = _bus_dmamap_create;
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dmat->_dmamap_destroy = _bus_dmamap_destroy;
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dmat->_dmamap_load = _bus_dmamap_load;
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dmat->_dmamap_load_mbuf = _bus_dmamap_load_mbuf;
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dmat->_dmamap_load_uio = _bus_dmamap_load_uio;
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dmat->_dmamap_load_raw = _bus_dmamap_load_raw;
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dmat->_dmamap_unload = _bus_dmamap_unload;
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dmat->_dmamap_sync_pre = _bus_dmamap_sync;
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dmat->_dmamap_sync_post = NULL;
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dmat->_dmamem_alloc = _bus_dmamem_alloc;
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dmat->_dmamem_free = _bus_dmamem_free;
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dmat->_dmamem_map = _bus_dmamem_map;
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dmat->_dmamem_unmap = _bus_dmamem_unmap;
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dmat->_dmamem_mmap = _bus_dmamem_mmap;
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}
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/*
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* i80321_local_dma_init:
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*
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* Initialize the local DMA tag.
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*/
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static void
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i80321_local_dma_init(struct i80321_softc *sc)
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{
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bus_dma_tag_t dmat = &sc->sc_local_dmat;
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dmat->_ranges = NULL;
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dmat->_nranges = 0;
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dmat->_dmamap_create = _bus_dmamap_create;
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dmat->_dmamap_destroy = _bus_dmamap_destroy;
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dmat->_dmamap_load = _bus_dmamap_load;
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dmat->_dmamap_load_mbuf = _bus_dmamap_load_mbuf;
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dmat->_dmamap_load_uio = _bus_dmamap_load_uio;
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dmat->_dmamap_load_raw = _bus_dmamap_load_raw;
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dmat->_dmamap_unload = _bus_dmamap_unload;
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dmat->_dmamap_sync_pre = _bus_dmamap_sync;
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dmat->_dmamap_sync_post = NULL;
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dmat->_dmamem_alloc = _bus_dmamem_alloc;
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dmat->_dmamem_free = _bus_dmamem_free;
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dmat->_dmamem_map = _bus_dmamem_map;
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dmat->_dmamem_unmap = _bus_dmamem_unmap;
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dmat->_dmamem_mmap = _bus_dmamem_mmap;
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}
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