0b6370bfee
this insn is available only on ARM arch v3 and later (and 2a). We don't expect to be using these ops in the kernel on processors too old to have SWP, and for userland uses (in e.g. a pthread library), the kernel will simply have to trap and emulate the insn (it needs to be "atomic", so a kernel trap of some sort will be necessary on such platforms anyway).
97 lines
3.2 KiB
C
97 lines
3.2 KiB
C
/* $NetBSD: lock.h,v 1.2 2001/11/15 19:22:32 thorpej Exp $ */
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/*-
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* Copyright (c) 2000, 2001 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Machine-dependent spin lock operations.
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*
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* NOTE: The SWP insn used here is available only on ARM architecture
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* version 3 and later (as well as 2a). What we are going to do is
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* expect that the kernel will trap and emulate the insn. That will
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* be slow, but give us the atomicity that we need.
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*/
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#ifndef _ARM_LOCK_H_
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#define _ARM_LOCK_H_
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typedef __volatile int __cpu_simple_lock_t;
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#define __SIMPLELOCK_LOCKED 1
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#define __SIMPLELOCK_UNLOCKED 0
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static __inline void __attribute__((__unused__))
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__cpu_simple_lock_init(__cpu_simple_lock_t *alp)
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{
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*alp = __SIMPLELOCK_UNLOCKED;
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}
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static __inline void __attribute__((__unused__))
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__cpu_simple_lock(__cpu_simple_lock_t *alp)
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{
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int __val = __SIMPLELOCK_LOCKED;
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do {
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__asm __volatile("swp %0, %1, [%2]"
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: "=r" (__val)
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: "0" (__val), "r" (alp)
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: "memory");
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} while (__val != __SIMPLELOCK_UNLOCKED);
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}
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static __inline int __attribute__((__unused__))
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__cpu_simple_lock_try(__cpu_simple_lock_t *alp)
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{
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int __val = __SIMPLELOCK_LOCKED;
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__asm __volatile("swp %0, %1, [%2]"
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: "=r" (__val)
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: "0" (__val), "r" (alp)
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: "memory");
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return ((__val == __SIMPLELOCK_UNLOCKED) ? 1 : 0);
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}
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static __inline void __attribute__((__unused__))
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__cpu_simple_unlock(__cpu_simple_lock_t *alp)
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{
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*alp = __SIMPLELOCK_UNLOCKED;
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}
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#endif /* _ARM_LOCK_H_ */
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