445 lines
10 KiB
C
445 lines
10 KiB
C
/* $NetBSD: emul.c,v 1.3 1997/07/29 09:42:01 fair Exp $ */
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/*
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* Copyright (c) 1997 Christos Zoulas. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Christos Zoulas.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/proc.h>
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#include <machine/reg.h>
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#include <machine/instr.h>
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#include <machine/cpu.h>
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#include <machine/psl.h>
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#include <sparc/sparc/cpuvar.h>
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#ifdef DEBUG_EMUL
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# define DPRINTF(a) uprintf a
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#else
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# define DPRINTF(a)
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#endif
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#define GPR(tf, i) ((int32_t *) &tf->tf_global)[i]
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#define IPR(tf, i) ((int32_t *) tf->tf_out[6])[i - 16]
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#define FPR(p, i) ((int32_t) p->p_md.md_fpstate->fs_regs[i])
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static __inline int readgpreg __P((struct trapframe *, int, void *));
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static __inline int readfpreg __P((struct proc *, int, void *));
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static __inline int writegpreg __P((struct trapframe *, int, const void *));
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static __inline int writefpreg __P((struct proc *, int, const void *));
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static __inline int decodeaddr __P((struct trapframe *, union instr *, void *));
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static int muldiv __P((struct trapframe *, union instr *, int32_t *, int32_t *,
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int32_t *));
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#define REGNAME(i) "goli"[i >> 3], i & 7
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static __inline int
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readgpreg(tf, i, val)
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struct trapframe *tf;
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int i;
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void *val;
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{
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int error = 0;
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if (i == 0)
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*(int32_t *) val = 0;
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else if (i < 16)
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*(int32_t *) val = GPR(tf, i);
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else
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error = copyin(&IPR(tf, i), val, sizeof(int32_t));
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return error;
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}
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static __inline int
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writegpreg(tf, i, val)
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struct trapframe *tf;
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int i;
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const void *val;
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{
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int error = 0;
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if (i == 0)
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return error;
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else if (i < 16)
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GPR(tf, i) = *(int32_t *) val;
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else
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/* XXX: Fix copyout prototype */
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error = copyout((caddr_t) val, &IPR(tf, i), sizeof(int32_t));
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return error;
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}
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static __inline int
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readfpreg(p, i, val)
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struct proc *p;
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int i;
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void *val;
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{
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*(int32_t *) val = FPR(p, i);
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return 0;
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}
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static __inline int
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writefpreg(p, i, val)
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struct proc *p;
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int i;
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const void *val;
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{
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FPR(p, i) = *(const int32_t *) val;
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return 0;
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}
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static __inline int
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decodeaddr(tf, code, val)
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struct trapframe *tf;
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union instr *code;
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void *val;
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{
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if (code->i_simm13.i_i)
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*((int32_t *) val) = code->i_simm13.i_simm13;
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else {
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int error;
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if (code->i_asi.i_asi)
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return EINVAL;
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if ((error = readgpreg(tf, code->i_asi.i_rs2, val)) != 0)
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return error;
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}
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return 0;
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}
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static int
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muldiv(tf, code, rd, rs1, rs2)
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struct trapframe *tf;
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union instr *code;
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int32_t *rd, *rs1, *rs2;
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{
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/*
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* We check for {S,U}{MUL,DIV}{,cc}
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*
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* [c = condition code, s = sign]
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* Mul = 0c101s
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* Div = 0c111s
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*/
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union {
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struct {
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unsigned unused:26; /* padding */
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unsigned zero:1; /* zero by opcode */
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unsigned cc:1; /* one to send condition code */
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unsigned one1:1; /* one by opcode */
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unsigned div:1; /* one if divide */
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unsigned one2:1; /* one by opcode */
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unsigned sgn:1; /* sign bit */
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} bits;
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int num;
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} op;
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op.num = code->i_op3.i_op3;
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#ifdef DEBUG_EMUL
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uprintf("muldiv 0x%x: %c%s%s %c%d, %c%d, ", code->i_int,
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"us"[op.bits.sgn], op.bits.div ? "div" : "mul",
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op.bits.cc ? "cc" : "", REGNAME(code->i_op3.i_rd),
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REGNAME(code->i_op3.i_rs1));
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if (code->i_loadstore.i_i)
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uprintf("0x%x\n", *rs2);
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else
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uprintf("%c%d\n", REGNAME(code->i_asi.i_rs2));
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#endif
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if (op.bits.div) {
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if (*rs2 == 0) {
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/*
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* XXX: to be 100% correct here, on sunos we need to
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* ignore the error and return *rd = *rs1.
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* It should be easy to fix by passing struct
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* proc in here.
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*/
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DPRINTF(("emulinstr: avoid zerodivide\n"));
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return EINVAL;
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}
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*rd = *rs1 / *rs2;
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DPRINTF(("muldiv: %d / %d = %d\n", *rs1, *rs2, *rd));
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}
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else {
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*rd = *rs1 * *rs2;
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DPRINTF(("muldiv: %d * %d = %d\n", *rs1, *rs2, *rd));
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}
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if (op.bits.cc) {
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/* Set condition codes */
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tf->tf_psr &= ~PSR_ICC;
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if (*rd == 0)
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tf->tf_psr |= PSR_Z << 20;
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else {
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if (op.bits.sgn && *rd < 0)
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tf->tf_psr |= PSR_N << 20;
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if (op.bits.div) {
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if (*rd * *rs2 != *rs1)
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tf->tf_psr |= PSR_O << 20;
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}
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else {
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if (*rd / *rs2 != *rs1)
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tf->tf_psr |= PSR_O << 20;
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}
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}
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}
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return 0;
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}
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/*
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* Code to handle alignment faults on the sparc. This is enabled by sending
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* a fixalign trap. Such code is generated by compiling with cc -misalign
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* on SunOS, but we don't have such a feature yet on our gcc.
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*/
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int
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fixalign(p, tf)
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struct proc *p;
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struct trapframe *tf;
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{
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static u_char sizedef[] = { 0x4, 0xff, 0x2, 0x8 };
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/*
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* This is particular to load and store instructions
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*/
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union {
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struct {
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unsigned unused:26; /* 26 padding */
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unsigned fl:1; /* 1 bit float flag */
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unsigned op:1; /* 1 bit opcode */
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unsigned sgn:1; /* 1 bit sign */
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unsigned st:1; /* 1 bit load/store */
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unsigned sz:2; /* 2 bit size register */
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} bits;
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int num;
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} op;
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union {
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double d;
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int32_t i[2];
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int16_t s[4];
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int8_t c[8];
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} data;
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union instr code;
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size_t size;
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int32_t rs1, rs2;
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int error;
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/* fetch and check the instruction that caused the fault */
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error = copyin((caddr_t) tf->tf_pc, &code.i_int, sizeof(code.i_int));
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if (error != 0) {
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DPRINTF(("fixalign: Bad instruction fetch\n"));
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return EINVAL;
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}
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/* Only support format 3 */
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if (code.i_any.i_op != 3) {
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DPRINTF(("fixalign: Not a load or store\n"));
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return EINVAL;
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}
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op.num = code.i_loadstore.i_op3;
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/* Check operand size */
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if ((size = sizedef[op.bits.sz]) == 0xff) {
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DPRINTF(("fixalign: Bad operand size\n"));
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return EINVAL;
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}
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write_user_windows();
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if ((error = readgpreg(tf, code.i_op3.i_rs1, &rs1)) != 0) {
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DPRINTF(("emulinstr: read rs1 %d\n", error));
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return error;
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}
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if ((error = decodeaddr(tf, &code, &rs2)) != 0) {
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DPRINTF(("emulinstr: decode addr %d\n", error));
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return error;
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}
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rs1 += rs2;
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#ifdef DEBUG_EMUL
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uprintf("memalign 0x%x: %s%c%c %c%d, %c%d, ", code.i_int,
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op.bits.st ? "st" : "ld", "us"[op.bits.sgn],
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"w*hd"[op.bits.sz], op.bits.fl ? 'f' : REGNAME(code.i_op3.i_rd),
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REGNAME(code.i_op3.i_rs1));
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if (code.i_loadstore.i_i)
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uprintf("0x%x\n", rs2);
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else
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uprintf("%c%d\n", REGNAME(code.i_asi.i_rs2));
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#endif
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#ifdef DIAGNOSTIC
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if (op.bits.fl && p != fpproc)
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panic("fp align without being the FP owning process");
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#endif
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if (op.bits.st) {
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if (op.bits.fl) {
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savefpstate(p->p_md.md_fpstate);
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error = readfpreg(p, code.i_op3.i_rd, &data.i[0]);
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if (error)
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return error;
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if (size == 8) {
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error = readfpreg(p, code.i_op3.i_rd + 1,
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&data.i[1]);
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if (error)
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return error;
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}
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}
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else {
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error = readgpreg(tf, code.i_op3.i_rd, &data.i[0]);
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if (error)
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return error;
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if (size == 8) {
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error = readgpreg(tf, code.i_op3.i_rd + 1,
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&data.i[1]);
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if (error)
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return error;
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}
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}
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if (size == 2)
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return copyout(&data.s[1], (caddr_t) rs1, size);
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else
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return copyout(&data.d, (caddr_t) rs1, size);
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}
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else { /* load */
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if (size == 2) {
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error = copyin((caddr_t) rs1, &data.s[1], size);
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if (error)
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return error;
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/* Sign extend if necessary */
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if (op.bits.sgn && (data.s[1] & 0x8000) != 0)
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data.s[0] = ~0;
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else
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data.s[0] = 0;
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}
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else
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error = copyin((caddr_t) rs1, &data.d, size);
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if (error)
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return error;
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if (op.bits.fl) {
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error = writefpreg(p, code.i_op3.i_rd, &data.i[0]);
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if (error)
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return error;
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if (size == 8) {
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error = writefpreg(p, code.i_op3.i_rd + 1,
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&data.i[1]);
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if (error)
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return error;
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}
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loadfpstate(p->p_md.md_fpstate);
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}
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else {
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error = writegpreg(tf, code.i_op3.i_rd, &data.i[0]);
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if (error)
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return error;
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if (size == 8)
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error = writegpreg(tf, code.i_op3.i_rd + 1,
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&data.i[1]);
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}
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}
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return error;
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}
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/*
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* Emulate unimplemented instructions on earlier sparc chips.
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*/
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int
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emulinstr(pc, tf)
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int pc;
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struct trapframe *tf;
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{
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union instr code;
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int32_t rs1, rs2, rd;
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int error;
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/* fetch and check the instruction that caused the fault */
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error = copyin((caddr_t) pc, &code.i_int, sizeof(code.i_int));
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if (error != 0) {
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DPRINTF(("emulinstr: Bad instruction fetch\n"));
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return SIGILL;
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}
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/* Only support format 2 */
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if (code.i_any.i_op != 2) {
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DPRINTF(("emulinstr: Not a format 2 instruction\n"));
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return SIGILL;
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}
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write_user_windows();
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if ((error = readgpreg(tf, code.i_op3.i_rs1, &rs1)) != 0) {
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DPRINTF(("emulinstr: read rs1 %d\n", error));
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return SIGILL;
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}
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if ((error = decodeaddr(tf, &code, &rs2)) != 0) {
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DPRINTF(("emulinstr: decode addr %d\n", error));
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return SIGILL;
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}
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switch (code.i_op3.i_op3) {
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case IOP3_FLUSH:
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cpuinfo.cache_flush((caddr_t)(rs1 + rs2), 4); /*XXX*/
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return 0;
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default:
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if ((code.i_op3.i_op3 & 0x2a) != 0xa) {
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DPRINTF(("emulinstr: Unsupported op3 0x%x\n",
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code.i_op3.i_op3));
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return SIGILL;
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}
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else if ((error = muldiv(tf, &code, &rd, &rs1, &rs2)) != 0)
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return SIGFPE;
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}
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if ((error = writegpreg(tf, code.i_op3.i_rd, &rd)) != 0) {
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DPRINTF(("muldiv: write rd %d\n", error));
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return SIGILL;
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}
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return 0;
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}
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