247 lines
10 KiB
C
247 lines
10 KiB
C
/* $NetBSD: cs4280reg.h,v 1.4 2001/02/07 14:41:11 tacha Exp $ */
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/*
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* Copyright (c) 1999, 2000 Tatoku Ogaito. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Tatoku Ogaito
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* for the NetBSD Project.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#define CS4280_BA0_SIZE 0x2000
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#define CS4280_BA1_SIZE 0x40000
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/* BA0 */
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/* Interrupt Reporting Registers */
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#define CS4280_HISR 0x000 /* Host Interrupt Status Register */
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#define HISR_INTENA 0x80000000
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#define HISR_MIDI 0x00100000
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#define HISR_CINT 0x00000002
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#define HISR_PINT 0x00000001
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#define CS4280_HICR 0x008 /* Host Interrupt Control Register */
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#define HICR_CHGM 0x00000002
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#define HICR_IEV 0x00000001
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/* Clock Control Registers */
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#define CS4280_CLKCR1 0x400 /* Clock Control Register 1 */
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#define CLKCR1_PLLSS_SPBC 0x00000000
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#define CLKCR1_PLLSS_RSV 0x00000004
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#define CLKCR1_PLLSS_PCI 0x00000008
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#define CLKCR1_PLLSS_RSV2 0x0000000c
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#define CLKCR1_PLLP 0x00000010
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#define CLKCR1_SWCE 0x00000020
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#define CS4280_CLKCR2 0x404 /* Clock Control Register 2 */
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#define CLKCR2_PDIVS_RSV 0x00000002
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#define CLKCR2_PDIVS_8 0x00000008
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#define CLKCR2_PDIVS_16 0x00000000
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#define CS4280_PLLM 0x408 /* PLL Multiplier Register */
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#define PLLM_STATE 0x0000003a
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#define CS4280_PLLCC 0x40c /* PLL Capacitor Coefficient Register */
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#define PLLCC_CDR_STATE 0x00000006
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#define PLLCC_LPF_STATE 0x00000078
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/* General Configuration Registers */
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#define CS4280_SERMC1 0x420 /* Serial Port Master Control Register 1 */
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#define SERMC1_MSPE 0x00000001
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#define SERMC1_PTC_MASK 0x0000000e
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#define SERMC1_PTC_CS423X 0x00000000
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#define SERMC1_PTC_AC97 0x00000002
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#define SERMC1_PLB_EN 0x00000010
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#define SERMC1_XLB_EN 0x00000020
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#define CS4280_SERC1 0x428 /* Serial Port Configuration Register 1 */
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#define SERC1_SO1EN 0x00000001
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#define SERC1_SO1F_MASK 0x0000000e
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#define SERC1_SO1F_CS423X 0x00000000
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#define SERC1_SO1F_AC97 0x00000002
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#define SERC1_SO1F_DAC 0x00000004
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#define SERC1_SO1F_SPDIF 0x00000006
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#define CS4280_SERC2 0x42c /* Serial Port Configuration Register 2 */
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#define SERC2_SI1EN 0x00000001
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#define SERC2_SI1F_MASK 0x0000000e
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#define SERC2_SI1F_CS423X 0x00000000
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#define SERC2_SI1F_AC97 0x00000002
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#define SERC2_SI1F_ADC 0x00000004
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#define SERC2_SI1F_SPDIF 0x00000006
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#define CS4280_SERBSP 0x43c
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#define SERBSP_FSP_MASK 0x0000000f
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#define CS4280_SERBST 0x440
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#define SERBST_RRDY 0x00000001
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#define SERBST_WBSY 0x00000002
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#define CS4280_SERBCM 0x444
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#define SERBCM_RDC 0x000000001
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#define SERBCM_WRC 0x000000002
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#define CS4280_SERBAD 0x448
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#define CS4280_SERBWP 0x450
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/*
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* AC97 Registers are moved to cs428xreg.h since
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* they are common for CS4280 and CS4281
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*/
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/* Host Access Methods */
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#define CS4280_GPIOR 0x4b8 /* General Purpose I/O Register */
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#define CS4280_EGPIODR 0x4bc /* Extended GPIO Direction Register */
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#define CS4280_EGPIOPTR 0x4c0 /* Extended GPIO Polarity/Type Register */
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#define CS4280_EGPIOTR 0x4c4 /* Extended GPIO Sticky Register */
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#define CS4280_EGPIOWR 0x4c8 /* Extended GPIO Wakeup Register */
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#define CS4280_EGPIOSR 0x4cc /* Extended GPIO Status Register */
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/* Control Register */
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#define CS4280_CFGI 0x4b0 /* Configuration Interface Register */
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#define CS4280_SERACC 0x4d8
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#define SERACC_CTYPE_MASK 0x00000001
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#define SERACC_CTYPE_1_03 0x00000000
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#define SERACC_CTYPE_2_0 0x00000001
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#define SERACC_TWO_CODECS 0x00000002
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#define SERACC_MDM 0x00000004
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#define SERACC_HSP 0x00000008
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/* Midi Port */
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#define CS4280_MIDCR 0x490 /* MIDI Control Register */
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#define MIDCR_TXE 0x00000001 /* MIDI Transmit Enable */
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#define MIDCR_RXE 0x00000002 /* MIDI Receive Enable */
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#define MIDCR_RIE 0x00000004 /* MIDI Receive Interrupt Enable */
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#define MIDCR_TIE 0x00000008 /* MIDI Transmit Interrupt Enable */
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#define MIDCR_MLB 0x00000010 /* MIDI Loop Back Enable */
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#define MIDCR_MRST 0x00000020 /* MIDI Reset */
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#define MIDCR_MASK 0x0000003f
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#define CS4280_MIDSR 0x494 /* Host MIDI Status Register */
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#define MIDSR_TBF 0x00000001 /* Transmit Buffer Full */
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#define MIDSR_RBE 0x00000002 /* Receive Buffer Empty */
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#define CS4280_MIDWP 0x498 /* MIDI Write Port */
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#define MIDWP_MASK 0x000000ff
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#define CS4280_MIDRP 0x49c /* MIDI Read Port */
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#define MIDRP_MASK 0x000000ff
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/* Joy Stick Port */
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#define CS4280_JSPT 0x480 /* Joystick Poll/Trigger Register */
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#define CS4280_JSCTL 0x484 /* Joystick Control Register */
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#define CS4280_JSC1 0x488 /* Joystick Coordinate Register 1 */
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#define CS4280_JSC2 0x48c /* Joystick Coordinate Register 2 */
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/* BA1 */
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/* Playback Parameters */
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#define CS4280_PDTC 0x00c0 /* Playback DMA Transaction Count */
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#define PDTC_MASK 0x000003ff
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#define CS4280_MK_PDTC(x) ((x)/2 - 1)
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#define CS4280_PFIE 0x00c4 /* Playback Format and Interrupt Enable */
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#define PFIE_UNSIGNED 0x00008000 /* Playback Format is unsigned */
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#define PFIE_SWAPPED 0x00004000 /* Playback Format is need swapped */
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#define PFIE_MONO 0x00002000 /* Playback Format is monoral */
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#define PFIE_8BIT 0x00001000 /* Playback Format is 8bit */
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#define PFIE_PI_ENABLE 0x00000000 /* Playback Interrupt Enabled */
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#define PFIE_PI_DISABLE 0x00000010 /* Playback Interrupt Disabled */
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#define PFIE_PI_MASK 0x0000003f
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#define PFIE_MASK 0x0000f03f
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#define CS4280_PBA 0x00c8 /* Playback Buffer Address */
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#define CS4280_PVOL 0x00f8 /* Playback Volume */
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#define CS4280_PSRC 0x0288 /* Playback Sample Rate Correction */
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#define PSRC_MASK 0xffff0000
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#define CS4280_MK_PSRC(psrc, py) ((((psrc) << 16) & 0xffff0000) | ((py) & 0xffff))
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#define CS4280_PCTL 0x02a4 /* Playback Control */
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#define PCTL_MASK 0xffff0000
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#define CS4280_PPI 0x02b4 /* Playback Phase Increment */
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/* Capture Parameters */
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#define CS4280_CCTL 0x0064 /* Capture Control */
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#define CCTL_MASK 0x0000ffff
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#define CS4280_CDTC 0x0100 /* Capture DMA Transaction Count */
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#define CS4280_CIE 0x0104 /* Capture Interrupt Enable */
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#define CIE_CI_ENABLE 0x00000001 /* Capture Interrupt enabled */
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#define CIE_CI_DISABLE 0x00000011 /* Capture Interrupt disabled */
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#define CIE_CI_MASK 0x0000003f
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#define CS4280_CBA 0x010c /* Capture Buffer Address */
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#define CS4280_CSRC 0x02c8 /* Capture Sample Rate Correction */
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#define CSRC_MASK 0xffff0000
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#define CS4280_MK_CSRC(csrc, cy) ((((csrc) << 16) & 0xffff0000) | ((cy) & 0xffff))
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#define CS4280_CCI 0x02d8 /* Capture Coefficient Increment */
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#define CCI_MASK 0xffff0000
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#define CS4280_CD 0x02e0 /* Capture Delay */
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#define CD_MASK 0xfffc000
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#define CS4280_CPI 0x02f4 /* Capture Phase Incremnt */
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#define CS4280_CGL 0x0134 /* Capture Group Length */
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#define CGL_MASK 0x0000ffff
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#define CS4280_CNT 0x0340 /* Capture Number of Triplets */
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#define CS4280_CGC 0x0138 /* Capture Group Count */
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#define CGC_MASK 0x0000ffff
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#define CS4280_CVOL 0x02f8 /* Capture Volume */
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/* Processor Registers */
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#define CS4280_SPCR 0x30000 /* Processor Control Register */
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#define SPCR_RUN 0x00000001
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#define SPCR_STPFR 0x00000002
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#define SPCR_RUNFR 0x00000004
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#define SPCR_DRQEN 0x00000020
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#define SPCR_RSTSP 0x00000040
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#define CS4280_DREG 0x30004
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#define CS4280_DSRWP 0x30008
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#define CS4280_TWPR 0x3000c /* Trap Write Port Register */
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#define CS4280_SPWR 0x30010
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#define CS4280_SPCS 0x30028 /* Processor Clock Status Register */
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#define SPCS_SPRUN 0x00000100
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#define CS4280_FRMT 0x30030 /* Frame Timer Register */
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#define FRMT_FTV 0x00000adf
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#define CF_MONO 0x01
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#define CF_8BIT 0x02
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#define CF_16BIT_STEREO 0x00
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#define CF_16BIT_MONO 0x01
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#define CF_8BIT_STEREO 0x02
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#define CF_8BIT_MONO 0x03
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#define MIDI_BUSY_WAIT 100
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#define MIDI_BUSY_DELAY 100 /* Delay when UART is busy */
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/* 3*1024 parameter, 3.5*1024 sample, 2*3.5*1024 code */
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#define BA1_DWORD_SIZE (13 * 1024 + 512)
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#define BA1_MEMORY_COUNT 3
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struct BA1struct {
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struct {
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u_int32_t offset;
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u_int32_t size;
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} memory[BA1_MEMORY_COUNT];
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u_int32_t map[BA1_DWORD_SIZE];
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};
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#define CS4280_ICHUNK 2048 /* Bytes between interrupts */
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#define CS4280_DCHUNK 4096 /* Bytes of DMA memory */
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#define CS4280_DALIGN 4096 /* Alignment of DMA memory */
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/* for AC97_REG_POWER */
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#define CS4280_POWER_DOWN_ALL 0x7f0f
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