339 lines
9.3 KiB
C
339 lines
9.3 KiB
C
/* $NetBSD: oiocsc.c,v 1.1 2009/02/10 06:04:56 rumble Exp $ */
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/*
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* Copyright (c) 2009 Stephen M. Rumble
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* Copyright (c) 2001 Wayne Knowles
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Wayne Knowles
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: oiocsc.c,v 1.1 2009/02/10 06:04:56 rumble Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/device.h>
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#include <sys/buf.h>
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#include <dev/scsipi/scsi_all.h>
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#include <dev/scsipi/scsipi_all.h>
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#include <dev/scsipi/scsiconf.h>
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#include <machine/cpu.h>
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#include <machine/bus.h>
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#include <machine/autoconf.h>
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#include <machine/machtype.h>
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#include <machine/sysconf.h>
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#include <sgimips/ioc/oiocreg.h>
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#include <sgimips/ioc/oiocvar.h>
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#include <dev/ic/wd33c93reg.h>
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#include <dev/ic/wd33c93var.h>
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#include <opt_kgdb.h>
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#include <sys/kgdb.h>
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struct oiocsc_softc {
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struct wd33c93_softc sc_wd33c93; /* Must be first */
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struct evcnt sc_intrcnt; /* Interrupt counter */
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bus_space_handle_t sc_sh;
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bus_space_tag_t sc_st;
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bus_dma_tag_t sc_dmat;
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bus_dmamap_t sc_dmamap;
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int sc_flags;
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#define WDSC_DMA_ACTIVE 0x1
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#define WDSC_DMA_MAPLOADED 0x2
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struct oioc_dma_softc {
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bus_space_tag_t sc_bst;
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bus_space_handle_t sc_bsh;
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bus_dma_tag_t sc_dmat;
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uint32_t sc_flags;
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uint32_t sc_dmalow;
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int sc_ndesc;
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bus_dmamap_t sc_dmamap;
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ssize_t sc_dlen; /* # bytes transfered */
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} sc_oiocdma;
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};
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void oiocsc_attach (device_t, device_t, void *);
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int oiocsc_match (device_t, struct cfdata *, void *);
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CFATTACH_DECL_NEW(oiocsc, sizeof(struct oiocsc_softc),
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oiocsc_match, oiocsc_attach, NULL, NULL);
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int oiocsc_dmasetup (struct wd33c93_softc *, void **, size_t *,
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int, size_t *);
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int oiocsc_dmago (struct wd33c93_softc *);
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void oiocsc_dmastop (struct wd33c93_softc *);
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void oiocsc_reset (struct wd33c93_softc *);
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int oiocsc_dmaintr (void *);
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int oiocsc_scsiintr (void *);
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/*
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* Always present on IP4, IP6, IP10.
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*/
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int
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oiocsc_match(device_t parent, struct cfdata *cf, void *aux)
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{
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struct oioc_attach_args *oa = aux;
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if (strcmp(oa->oa_name, cf->cf_name) == 0)
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return (1);
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return (0);
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}
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/*
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* Attach the wdsc driver
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*/
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void
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oiocsc_attach(device_t parent, device_t self, void *aux)
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{
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struct oiocsc_softc *osc = device_private(self);
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struct wd33c93_softc *sc = &osc->sc_wd33c93;
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struct oioc_attach_args *oa = aux;
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int err;
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sc->sc_dev = self;
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sc->sc_regt = oa->oa_st;
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osc->sc_st = oa->oa_st;
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osc->sc_sh = oa->oa_sh;
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osc->sc_dmat = oa->oa_dmat;
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if ((err = bus_space_subregion(oa->oa_st, oa->oa_sh, OIOC_WD33C93_ASR,
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OIOC_WD33C93_ASR_SIZE, &sc->sc_asr_regh)) != 0) {
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printf(": unable to map regs, err=%d\n", err);
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return;
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}
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if ((err = bus_space_subregion(oa->oa_st, oa->oa_sh, OIOC_WD33C93_DATA,
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OIOC_WD33C93_DATA_SIZE, &sc->sc_data_regh)) != 0) {
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printf(": unable to map regs, err=%d\n", err);
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return;
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}
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if (bus_dmamap_create(osc->sc_dmat,
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OIOC_SCSI_DMA_NSEGS * PAGE_SIZE,
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OIOC_SCSI_DMA_NSEGS, PAGE_SIZE, PAGE_SIZE,
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BUS_DMA_WAITOK, &osc->sc_dmamap) != 0) {
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printf(": failed to create dmamap\n");
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return;
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}
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sc->sc_dmasetup = oiocsc_dmasetup;
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sc->sc_dmago = oiocsc_dmago;
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sc->sc_dmastop = oiocsc_dmastop;
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sc->sc_reset = oiocsc_reset;
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sc->sc_adapter.adapt_request = wd33c93_scsi_request;
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sc->sc_adapter.adapt_minphys = minphys;
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sc->sc_id = 0; /* Host ID = 0 */
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sc->sc_clkfreq = 100; /* 10MHz */
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/* Disable DMA - it's not ready for prime time, see oiocsc_dmasetup */
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#if 0
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sc->sc_dmamode = (oa->oa_burst_dma) ?
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SBIC_CTL_BURST_DMA : SBIC_CTL_DMA;
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#else
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sc->sc_dmamode = 0;
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#endif
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evcnt_attach_dynamic(&osc->sc_intrcnt, EVCNT_TYPE_INTR, NULL,
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device_xname(sc->sc_dev), "intr");
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if ((cpu_intr_establish(oa->oa_irq, IPL_BIO,
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oiocsc_scsiintr, sc)) == NULL) {
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printf(": unable to establish interrupt!\n");
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return;
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}
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wd33c93_attach(sc);
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}
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/*
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* Prime the hardware for a DMA transfer
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*
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* Requires splbio() interrupts to be disabled by the caller
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*
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* XXX- I'm not sure if this works properly yet. Primarily, I'm not sure
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* that all ds_addr's after the first will be page aligned. If they're
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* not, we apparently cannot use this DMA engine...
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*
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* Unfortunately, I'm getting mutex panics while testing with EFS (haven't
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* tried FFS), so I cannot yet confirm whether this works or not.
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*/
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int
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oiocsc_dmasetup(struct wd33c93_softc *dev, void **addr, size_t *len, int datain,
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size_t *dmasize)
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{
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struct oiocsc_softc *osc = (void *)dev;
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struct oioc_dma_softc *dsc = &osc->sc_oiocdma;
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int count, err, i;
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void *vaddr;
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KASSERT((osc->sc_flags & WDSC_DMA_ACTIVE) == 0);
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vaddr = *addr;
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count = dsc->sc_dlen = *len;
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if (count) {
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bus_dmamap_t dmamap = osc->sc_dmamap;
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KASSERT((osc->sc_flags & WDSC_DMA_MAPLOADED) == 0);
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/* Build list of physical addresses for this transfer */
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if ((err = bus_dmamap_load(osc->sc_dmat, osc->sc_dmamap,
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vaddr, count,
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NULL /* kernel address */,
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BUS_DMA_NOWAIT)) != 0)
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panic("%s: bus_dmamap_load err=%d",
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device_xname(dev->sc_dev), err);
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/*
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* We can map the contiguous buffer with up to 256 pages.
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* The DMA low address register contains a 12-bit offset for
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* the first page (in case the buffer isn't aligned). The 256
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* high registers contain 16 bits each for page numbers.
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*
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* We will fill in the high registers here. The low register
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* fires off the DMA engine and is set in oiocsc_dmago.
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*/
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dsc->sc_dmalow = dmamap->dm_segs[0].ds_addr &
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OIOC_SCSI_DMA_LOW_ADDR_MASK;
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KASSERT(dmamap->dm_nsegs <= OIOC_SCSI_DMA_NSEGS);
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for (i = 0; i < dmamap->dm_nsegs; i++) {
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uint16_t pgnum;
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pgnum = dmamap->dm_segs[i].ds_addr >>
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OIOC_SCSI_DMA_HIGH_SHFT;
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bus_space_write_2(osc->sc_st, osc->sc_sh,
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OIOC_SCSI_DMA_HIGH(i), pgnum);
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}
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osc->sc_flags |= WDSC_DMA_MAPLOADED;
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if (datain)
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dsc->sc_dmalow |= OIOC_SCSI_DMA_LOW_ADDR_DMADIR;
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}
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return (count);
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}
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/*
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* Prime the hardware for the next DMA transfer
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*/
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int
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oiocsc_dmago(struct wd33c93_softc *dev)
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{
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struct oiocsc_softc *osc = (void *)dev;
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struct oioc_dma_softc *dsc = &osc->sc_oiocdma;
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if (dsc->sc_dlen == 0)
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return(0);
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KASSERT((osc->sc_flags & WDSC_DMA_ACTIVE) == 0);
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KASSERT((osc->sc_flags & WDSC_DMA_MAPLOADED));
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osc->sc_flags |= WDSC_DMA_ACTIVE;
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bus_dmamap_sync(osc->sc_dmat, osc->sc_dmamap, 0,
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osc->sc_dmamap->dm_mapsize,
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BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
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/* Blastoff! */
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bus_space_write_2(osc->sc_st, osc->sc_sh,
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OIOC_SCSI_DMA_LOW, dsc->sc_dmalow);
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return(osc->sc_dmamap->dm_mapsize);
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}
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/*
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* Stop DMA and unload active DMA maps
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*/
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void
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oiocsc_dmastop(struct wd33c93_softc *dev)
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{
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struct oiocsc_softc *osc = (void *)dev;
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if (osc->sc_flags & WDSC_DMA_ACTIVE) {
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/* Stop DMA, flush and sync */
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bus_space_write_4(osc->sc_st, osc->sc_sh,
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OIOC_SCSI_DMA_FLUSH, 0);
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bus_dmamap_sync(osc->sc_dmat, osc->sc_dmamap, 0,
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osc->sc_dmamap->dm_mapsize,
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BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
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}
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if (osc->sc_flags & WDSC_DMA_MAPLOADED)
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bus_dmamap_unload(osc->sc_dmat, osc->sc_dmamap);
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osc->sc_flags &= ~(WDSC_DMA_ACTIVE | WDSC_DMA_MAPLOADED);
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}
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/*
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* Reset the controller.
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*/
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void
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oiocsc_reset(struct wd33c93_softc *dev)
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{
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struct oiocsc_softc *osc = (void *)dev;
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/* hard reset the chip */
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bus_space_read_4(osc->sc_st, osc->sc_sh, OIOC_SCSI_RESET_ON);
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delay(1000);
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bus_space_read_4(osc->sc_st, osc->sc_sh, OIOC_SCSI_RESET_OFF);
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delay(1000);
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}
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/*
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* WD33c93 SCSI controller interrupt
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*/
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int
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oiocsc_scsiintr(void *arg)
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{
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struct wd33c93_softc *dev = arg;
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struct oiocsc_softc *osc = arg;
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int found;
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found = wd33c93_intr(dev);
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if (found)
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osc->sc_intrcnt.ev_count++;
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return(found);
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}
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