365 lines
9.4 KiB
C
365 lines
9.4 KiB
C
/* $NetBSD: pci_6600.c,v 1.5 2000/06/06 00:50:15 thorpej Exp $ */
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/*-
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* Copyright (c) 1999 by Ross Harvey. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Ross Harvey.
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* 4. The name of Ross Harvey may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY ROSS HARVEY ``AS IS'' AND ANY EXPRESS
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* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURP0SE
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* ARE DISCLAIMED. IN NO EVENT SHALL ROSS HARVEY BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: pci_6600.c,v 1.5 2000/06/06 00:50:15 thorpej Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/device.h>
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#include <sys/malloc.h>
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#include <vm/vm.h>
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#include <machine/autoconf.h>
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#define _ALPHA_BUS_DMA_PRIVATE
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#include <machine/bus.h>
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#include <machine/rpb.h>
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#include <machine/alpha.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pciidereg.h>
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#include <dev/pci/pciidevar.h>
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#include <alpha/pci/tsreg.h>
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#include <alpha/pci/tsvar.h>
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#include <alpha/pci/pci_6600.h>
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#define pci_6600() { Generate ctags(1) key. }
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#include "sio.h"
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#if NSIO
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#include <alpha/pci/siovar.h>
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#endif
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#define PCI_NIRQ 64
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#define PCI_STRAY_MAX 5
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/*
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* Some Tsunami models have a PCI device (the USB controller) with interrupts
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* tied to ISA IRQ lines. The IRQ is encoded as:
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*
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* line = 0xe0 | isa_irq;
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*/
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#define DEC_6600_LINE_IS_ISA(line) ((line) >= 0xe0 && (line) <= 0xef)
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#define DEC_6600_LINE_ISA_IRQ(line) ((line) & 0x0f)
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static char *irqtype = "6600 irq";
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static struct tsp_config *sioprimary;
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void dec_6600_intr_disestablish __P((void *, void *));
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void *dec_6600_intr_establish __P((
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void *, pci_intr_handle_t, int, int (*func)(void *), void *));
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const char *dec_6600_intr_string __P((void *, pci_intr_handle_t));
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const struct evcnt *dec_6600_intr_evcnt __P((void *, pci_intr_handle_t));
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int dec_6600_intr_map __P((void *, pcitag_t, int, int, pci_intr_handle_t *));
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void *dec_6600_pciide_compat_intr_establish __P((void *, struct device *,
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struct pci_attach_args *, int, int (*)(void *), void *));
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struct alpha_shared_intr *dec_6600_pci_intr;
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void dec_6600_iointr __P((void *framep, unsigned long vec));
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extern void dec_6600_intr_enable __P((int irq));
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extern void dec_6600_intr_disable __P((int irq));
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void
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pci_6600_pickintr(pcp)
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struct tsp_config *pcp;
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{
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bus_space_tag_t iot = &pcp->pc_iot;
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pci_chipset_tag_t pc = &pcp->pc_pc;
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char *cp;
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int i;
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pc->pc_intr_v = pcp;
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pc->pc_intr_map = dec_6600_intr_map;
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pc->pc_intr_string = dec_6600_intr_string;
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pc->pc_intr_evcnt = dec_6600_intr_evcnt;
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pc->pc_intr_establish = dec_6600_intr_establish;
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pc->pc_intr_disestablish = dec_6600_intr_disestablish;
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pc->pc_pciide_compat_intr_establish = NULL;
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/*
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* System-wide and Pchip-0-only logic...
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*/
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if (dec_6600_pci_intr == NULL) {
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sioprimary = pcp;
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pc->pc_pciide_compat_intr_establish =
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dec_6600_pciide_compat_intr_establish;
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dec_6600_pci_intr = alpha_shared_intr_alloc(PCI_NIRQ, 8);
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for (i = 0; i < PCI_NIRQ; i++) {
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alpha_shared_intr_set_maxstrays(dec_6600_pci_intr, i,
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PCI_STRAY_MAX);
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alpha_shared_intr_set_private(dec_6600_pci_intr, i,
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sioprimary);
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cp = alpha_shared_intr_string(dec_6600_pci_intr, i);
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sprintf(cp, "irq %d", i);
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evcnt_attach_dynamic(alpha_shared_intr_evcnt(
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dec_6600_pci_intr, 1), EVCNT_TYPE_INTR, NULL,
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"dec_6600", cp);
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}
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#if NSIO
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sio_intr_setup(pc, iot);
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dec_6600_intr_enable(55); /* irq line for sio */
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#endif
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set_iointr(dec_6600_iointr);
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}
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}
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int
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dec_6600_intr_map(acv, bustag, buspin, line, ihp)
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void *acv;
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pcitag_t bustag;
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int buspin, line;
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pci_intr_handle_t *ihp;
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{
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struct tsp_config *pcp = acv;
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pci_chipset_tag_t pc = &pcp->pc_pc;
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int bus, device, function;
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if (buspin == 0) {
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/* No IRQ used. */
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return 1;
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}
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if (buspin > 4) {
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printf("intr_map: bad interrupt pin %d\n", buspin);
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return 1;
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}
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alpha_pci_decompose_tag(pc, bustag, &bus, &device, &function);
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/*
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* The console places the interrupt mapping in the "line" value.
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* A value of (char)-1 indicates there is no mapping.
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*/
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if (line == 0xff) {
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printf("dec_6600_intr_map: no mapping for %d/%d/%d\n",
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bus, device, function);
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return (1);
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}
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#if NSIO == 0
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if (DEC_6600_LINE_IS_ISA(line)) {
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printf("dec_6600_intr_map: ISA IRQ %d for %d/%d/%d\n",
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DEC_6600_LINE_ISA_IRQ(line), bus, device, function);
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return (1);
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}
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#endif
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if (DEC_6600_LINE_IS_ISA(line) == 0 && line >= PCI_NIRQ)
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panic("dec_6600_intr_map: dec 6600 irq too large (%d)\n",
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line);
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*ihp = line;
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return (0);
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}
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const char *
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dec_6600_intr_string(acv, ih)
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void *acv;
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pci_intr_handle_t ih;
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{
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static const char irqfmt[] = "dec 6600 irq %ld";
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static char irqstr[sizeof irqfmt];
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#if NSIO
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if (DEC_6600_LINE_IS_ISA(ih))
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return (sio_intr_string(NULL /*XXX*/,
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DEC_6600_LINE_ISA_IRQ(ih)));
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#endif
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snprintf(irqstr, sizeof irqstr, irqfmt, ih);
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return (irqstr);
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}
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const struct evcnt *
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dec_6600_intr_evcnt(acv, ih)
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void *acv;
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pci_intr_handle_t ih;
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{
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#if NSIO
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if (DEC_6600_LINE_IS_ISA(ih))
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return (sio_intr_evcnt(NULL /*XXX*/,
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DEC_6600_LINE_ISA_IRQ(ih)));
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#endif
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return (alpha_shared_intr_evcnt(dec_6600_pci_intr, ih));
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}
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void *
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dec_6600_intr_establish(acv, ih, level, func, arg)
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void *acv, *arg;
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pci_intr_handle_t ih;
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int level;
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int (*func) __P((void *));
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{
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void *cookie;
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#if NSIO
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if (DEC_6600_LINE_IS_ISA(ih))
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return (sio_intr_establish(NULL /*XXX*/,
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DEC_6600_LINE_ISA_IRQ(ih), IST_LEVEL, level, func, arg));
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#endif
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if (ih >= PCI_NIRQ)
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panic("dec_6600_intr_establish: bogus dec 6600 IRQ 0x%lx\n",
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ih);
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cookie = alpha_shared_intr_establish(dec_6600_pci_intr, ih, IST_LEVEL,
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level, func, arg, irqtype);
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if (cookie != NULL && alpha_shared_intr_isactive(dec_6600_pci_intr, ih))
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dec_6600_intr_enable(ih);
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return (cookie);
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}
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void
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dec_6600_intr_disestablish(acv, cookie)
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void *acv, *cookie;
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{
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struct alpha_shared_intrhand *ih = cookie;
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unsigned int irq = ih->ih_num;
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int s;
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#if NSIO
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/*
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* We have to determine if this is an ISA IRQ or not! We do this
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* by checking to see if the intrhand points back to an intrhead
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* that points to the sioprimary TSP. If not, it's an ISA IRQ.
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* Pretty disgusting, eh?
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*/
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if (ih->ih_intrhead->intr_private != sioprimary) {
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sio_intr_disestablish(NULL /*XXX*/, cookie);
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return;
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}
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#endif
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s = splhigh();
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alpha_shared_intr_disestablish(dec_6600_pci_intr, cookie, irqtype);
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if (alpha_shared_intr_isactive(dec_6600_pci_intr, irq) == 0) {
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dec_6600_intr_disable(irq);
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alpha_shared_intr_set_dfltsharetype(dec_6600_pci_intr, irq,
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IST_NONE);
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}
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splx(s);
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}
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void
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dec_6600_iointr(framep, vec)
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void *framep;
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unsigned long vec;
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{
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int irq;
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if (vec >= 0x900) {
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irq = (vec - 0x900) >> 4;
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if (irq >= PCI_NIRQ)
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panic("iointr: irq %d is too high", irq);
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if (!alpha_shared_intr_dispatch(dec_6600_pci_intr, irq)) {
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alpha_shared_intr_stray(dec_6600_pci_intr, irq,
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irqtype);
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if (ALPHA_SHARED_INTR_DISABLE(dec_6600_pci_intr, irq))
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dec_6600_intr_disable(irq);
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}
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return;
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}
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#if NSIO
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if (vec >= 0x800) {
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sio_iointr(framep, vec);
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return;
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}
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#endif
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panic("iointr: weird vec 0x%lx\n", vec);
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}
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void
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dec_6600_intr_enable(irq)
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int irq;
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{
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alpha_mb();
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STQP(TS_C_DIM0) |= 1UL << irq;
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alpha_mb();
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}
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void
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dec_6600_intr_disable(irq)
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int irq;
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{
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alpha_mb();
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STQP(TS_C_DIM0) &= ~(1UL << irq);
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alpha_mb();
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}
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void *
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dec_6600_pciide_compat_intr_establish(v, dev, pa, chan, func, arg)
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void *v;
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struct device *dev;
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struct pci_attach_args *pa;
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int chan;
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int (*func) __P((void *));
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void *arg;
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{
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pci_chipset_tag_t pc = pa->pa_pc;
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void *cookie = NULL;
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int bus, irq;
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alpha_pci_decompose_tag(pc, pa->pa_tag, &bus, NULL, NULL);
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/*
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* If this isn't PCI bus #0 on the TSP that holds the PCI-ISA
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* bridge, all bets are off.
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*/
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if (bus != 0 || pc->pc_intr_v != sioprimary)
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return (NULL);
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irq = PCIIDE_COMPAT_IRQ(chan);
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#if NSIO
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cookie = sio_intr_establish(NULL /*XXX*/, irq, IST_EDGE, IPL_BIO,
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func, arg);
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if (cookie == NULL)
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return (NULL);
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printf("%s: %s channel interrupting at %s\n", dev->dv_xname,
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PCIIDE_CHANNEL_NAME(chan), sio_intr_string(NULL /*XXX*/, irq));
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#endif
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return (cookie);
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}
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