1657 lines
39 KiB
C
1657 lines
39 KiB
C
/* $NetBSD: cpu.c,v 1.116 2001/03/16 10:26:11 mrg Exp $ */
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/*
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* Copyright (c) 1996
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* The President and Fellows of Harvard College. All rights reserved.
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This software was developed by the Computer Systems Engineering group
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* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
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* contributed to Berkeley.
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*
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* All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Harvard University.
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* This product includes software developed by the University of
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* California, Lawrence Berkeley Laboratory.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Aaron Brown and
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* Harvard University.
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)cpu.c 8.5 (Berkeley) 11/23/93
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*
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*/
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#include "opt_multiprocessor.h"
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#include "opt_ddb.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <sys/malloc.h>
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#include <uvm/uvm.h>
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#include <machine/autoconf.h>
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#include <machine/cpu.h>
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#include <machine/reg.h>
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#include <machine/ctlreg.h>
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#include <machine/trap.h>
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#include <machine/pcb.h>
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#include <machine/pmap.h>
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#include <machine/oldmon.h>
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#include <machine/idprom.h>
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#include <sparc/sparc/cache.h>
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#include <sparc/sparc/asm.h>
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#include <sparc/sparc/cpuvar.h>
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#include <sparc/sparc/memreg.h>
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struct cpu_softc {
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struct device sc_dv; /* generic device info */
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struct cpu_info *sc_cpuinfo;
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};
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/* The following are used externally (sysctl_hw). */
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char machine[] = MACHINE; /* from <machine/param.h> */
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char machine_arch[] = MACHINE_ARCH; /* from <machine/param.h> */
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char cpu_model[100];
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int ncpu; /* # of CPUs detected by PROM */
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struct cpu_info **cpus;
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#define CPU_MID2CPUNO(mid) ((mid) - 8)
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static int cpu_instance; /* current # of CPUs wired by us */
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/* The CPU configuration driver. */
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static void cpu_attach __P((struct device *, struct device *, void *));
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int cpu_match __P((struct device *, struct cfdata *, void *));
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struct cfattach cpu_ca = {
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sizeof(struct cpu_softc), cpu_match, cpu_attach
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};
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static char *fsrtoname __P((int, int, int));
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void cache_print __P((struct cpu_softc *));
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void cpu_setup __P((struct cpu_softc *));
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void cpu_spinup __P((struct cpu_softc *));
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void fpu_init __P((struct cpu_info *));
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#define IU_IMPL(psr) ((u_int)(psr) >> 28)
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#define IU_VERS(psr) (((psr) >> 24) & 0xf)
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#define SRMMU_IMPL(mmusr) ((u_int)(mmusr) >> 28)
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#define SRMMU_VERS(mmusr) (((mmusr) >> 24) & 0xf)
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#if defined(MULTIPROCESSOR)
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struct cpu_info *alloc_cpuinfo_global_va __P((int, vsize_t *));
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struct cpu_info *alloc_cpuinfo __P((void));
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struct cpu_info *
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alloc_cpuinfo_global_va(ismaster, sizep)
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int ismaster;
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vsize_t *sizep;
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{
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int align;
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vaddr_t sva, va;
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vsize_t sz, esz;
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/*
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* Allocate aligned KVA. `cpuinfo' resides at a fixed virtual
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* address. Since we need to access an other CPU's cpuinfo
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* structure occasionally, this must be done at a virtual address
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* that's cache congruent to the fixed address CPUINFO_VA.
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*
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* NOTE: we're using the cache properties of the boot CPU to
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* determine the alignment (XXX).
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*/
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align = NBPG;
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if (CACHEINFO.c_totalsize > align)
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/* Assumes `c_totalsize' is power of two */
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align = CACHEINFO.c_totalsize;
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sz = sizeof(struct cpu_info);
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if (ismaster == 0) {
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/*
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* While we're here, allocate a per-CPU idle PCB and
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* interrupt stack as well.
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*/
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sz += USPACE; /* `idle' u-area for this CPU */
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sz += INT_STACK_SIZE; /* interrupt stack for this CPU */
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}
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sz = (sz + NBPG - 1) & -NBPG;
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esz = sz + align - NBPG;
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if ((sva = uvm_km_valloc(kernel_map, esz)) == 0)
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panic("alloc_cpuinfo_global_va: no virtual space");
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va = sva + (((CPUINFO_VA & (align - 1)) + align - sva) & (align - 1));
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/* Return excess virtual memory space */
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if (va != sva)
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(void)uvm_unmap(kernel_map, sva, va);
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if (va + sz != sva + esz)
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(void)uvm_unmap(kernel_map, va + sz, sva + esz);
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if (sizep != NULL)
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*sizep = sz;
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return ((struct cpu_info *)va);
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}
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struct cpu_info *
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alloc_cpuinfo()
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{
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vaddr_t va;
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vsize_t sz;
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vaddr_t low, high;
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vm_page_t m;
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struct pglist mlist;
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struct cpu_info *cpi;
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/* Allocate the aligned VA and determine the size. */
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cpi = alloc_cpuinfo_global_va(0, &sz);
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va = (vaddr_t)cpi;
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/* Allocate physical pages */
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low = vm_first_phys;
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high = vm_first_phys + vm_num_phys - NBPG;
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TAILQ_INIT(&mlist);
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if (uvm_pglistalloc(sz, low, high, NBPG, 0, &mlist, 1, 0) != 0)
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panic("alloc_cpuinfo: no pages");
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/* Map the pages */
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for (m = TAILQ_FIRST(&mlist); m != NULL; m = TAILQ_NEXT(m, pageq)) {
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paddr_t pa = VM_PAGE_TO_PHYS(m);
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pmap_enter(pmap_kernel(), va, pa,
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VM_PROT_READ|VM_PROT_WRITE,
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VM_PROT_READ|VM_PROT_WRITE|PMAP_WIRED);
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va += NBPG;
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}
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bzero((void *)cpi, sz);
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cpi->eintstack = (void *)((vaddr_t)cpi + sz);
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cpi->idle_u = (void *)((vaddr_t)cpi + sz - INT_STACK_SIZE - USPACE);
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return (cpi);
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}
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#endif /* MULTIPROCESSOR */
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#ifdef notdef
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/*
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* IU implementations are parceled out to vendors (with some slight
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* glitches). Printing these is cute but takes too much space.
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*/
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static char *iu_vendor[16] = {
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"Fujitsu", /* and also LSI Logic */
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"ROSS", /* ROSS (ex-Cypress) */
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"BIT",
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"LSIL", /* LSI Logic finally got their own */
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"TI", /* Texas Instruments */
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"Matsushita",
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"Philips",
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"Harvest", /* Harvest VLSI Design Center */
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"SPEC", /* Systems and Processes Engineering Corporation */
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"Weitek",
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"vendor#10",
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"vendor#11",
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"vendor#12",
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"vendor#13",
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"vendor#14",
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"vendor#15"
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};
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#endif
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/*
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* 4/110 comment: the 4/110 chops off the top 4 bits of an OBIO address.
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* this confuses autoconf. for example, if you try and map
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* 0xfe000000 in obio space on a 4/110 it actually maps 0x0e000000.
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* this is easy to verify with the PROM. this causes problems
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* with devices like "esp0 at obio0 addr 0xfa000000" because the
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* 4/110 treats it as esp0 at obio0 addr 0x0a000000" which is the
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* address of the 4/110's "sw0" scsi chip. the same thing happens
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* between zs1 and zs2. since the sun4 line is "closed" and
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* we know all the "obio" devices that will ever be on it we just
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* put in some special case "if"'s in the match routines of esp,
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* dma, and zs.
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*/
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int
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cpu_match(parent, cf, aux)
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struct device *parent;
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struct cfdata *cf;
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void *aux;
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{
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struct mainbus_attach_args *ma = aux;
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return (strcmp(cf->cf_driver->cd_name, ma->ma_name) == 0);
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}
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/*
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* Attach the CPU.
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* Discover interesting goop about the virtual address cache
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* (slightly funny place to do it, but this is where it is to be found).
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*/
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static void
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cpu_attach(parent, self, aux)
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struct device *parent;
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struct device *self;
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void *aux;
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{
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static struct cpu_softc *bootcpu;
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struct mainbus_attach_args *ma = aux;
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struct cpu_softc *sc = (struct cpu_softc *)self;
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struct cpu_info *cpi;
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int node, mid;
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node = ma->ma_node;
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#if defined(MULTIPROCESSOR)
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mid = (node != 0) ? getpropint(node, "mid", 0) : 0;
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#else
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mid = 0;
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#endif
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/*
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* First, find out if we're attaching the boot CPU.
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*/
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if (bootcpu == NULL) {
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extern struct pcb idle_u[];
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bootcpu = sc;
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cpus = malloc(ncpu * sizeof(cpi), M_DEVBUF, M_NOWAIT);
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bzero(cpus, ncpu * sizeof(cpi));
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getcpuinfo(&cpuinfo, node);
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#if defined(MULTIPROCESSOR)
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/*
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* Allocate a suitable global VA for the boot CPU's
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* cpu_info (which is already statically allocated),
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* and double map it to that global VA. Then fixup
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* the self-reference to use the globalized address.
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*/
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cpi = sc->sc_cpuinfo = alloc_cpuinfo_global_va(1, NULL);
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pmap_globalize_boot_cpuinfo(cpi);
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cpuinfo.ci_self = cpi;
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/* XXX - fixup proc0.p_cpu */
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proc0.p_cpu = cpi;
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#else
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/* The `local' VA is global for uniprocessor. */
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cpi = sc->sc_cpuinfo = (struct cpu_info *)CPUINFO_VA;
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#endif
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cpi->master = 1;
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cpi->eintstack = eintstack;
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cpi->idle_u = idle_u;
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/* Note: `curpcb' is set to `proc0' in locore */
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} else {
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#if defined(MULTIPROCESSOR)
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cpi = sc->sc_cpuinfo = alloc_cpuinfo();
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cpi->ci_self = cpi;
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cpi->curpcb = cpi->idle_u;
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cpi->curpcb->pcb_wim = 1;
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/*
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* Note: `idle_u' and `eintstack' are set in alloc_cpuinfo().
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* The %wim register will be initialized in cpu_hatch().
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*/
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getcpuinfo(cpi, node);
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#else
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printf(": no SMP support in kernel\n");
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return;
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#endif
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}
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#ifdef DEBUG
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cpi->redzone = (void *)((long)cpi->idle_u + REDSIZE);
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#endif
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cpus[cpu_instance] = cpi;
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cpi->ci_cpuid = cpu_instance++;
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cpi->mid = mid;
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cpi->node = node;
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simple_lock_init(&cpi->msg.lock);
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if (ncpu > 1)
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printf(": mid %d", mid);
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if (cpi->master) {
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cpu_setup(sc);
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sprintf(cpu_model, "%s @ %s MHz, %s FPU",
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cpi->cpu_name, clockfreq(cpi->hz), cpi->fpu_name);
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printf(": %s\n", cpu_model);
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cache_print(sc);
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return;
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}
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#if defined(MULTIPROCESSOR)
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/* for now use the fixed virtual addresses setup in autoconf.c */
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cpi->intreg_4m = (struct icr_pi *)
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(PI_INTR_VA + (_MAXNBPG * CPU_MID2CPUNO(mid)));
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/* Now start this CPU */
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cpu_spinup(sc);
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printf(": %s @ %s MHz, %s FPU\n", cpi->cpu_name,
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clockfreq(cpi->hz), cpi->fpu_name);
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cache_print(sc);
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if (ncpu > 1 && cpu_instance == ncpu) {
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int n;
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/*
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* Install MP cache flush functions, unless the
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* single-processor versions are no-ops.
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*/
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for (n = 0; n < ncpu; n++) {
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struct cpu_info *cpi = cpus[n];
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if (cpi == NULL)
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continue;
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#define SET_CACHE_FUNC(x) \
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if (cpi->x != __CONCAT(noop_,x)) cpi->x = __CONCAT(smp_,x)
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SET_CACHE_FUNC(cache_flush);
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SET_CACHE_FUNC(vcache_flush_page);
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SET_CACHE_FUNC(vcache_flush_segment);
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SET_CACHE_FUNC(vcache_flush_region);
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SET_CACHE_FUNC(vcache_flush_context);
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}
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}
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#endif /* MULTIPROCESSOR */
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}
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#if defined(MULTIPROCESSOR)
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/*
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* Start secondary processors in motion.
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*/
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void
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cpu_boot_secondary_processors()
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{
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/*
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* XXX This is currently a noop; the CPUs are already running, but
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* XXX aren't doing anything. Eventually, this will release a
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* XXX semaphore that all those secondary processors are anxiously
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* XXX waiting on.
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*/
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if (cpu_instance != ncpu) {
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printf("NOTICE: only %d out of %d CPUs were configured\n",
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cpu_instance, ncpu);
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return;
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}
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}
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#endif /* MULTIPROCESSOR */
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/* */
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void *cpu_hatchstack = 0;
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void *cpu_hatch_sc = 0;
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volatile int cpu_hatched = 0;
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/*
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* Finish CPU attach.
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* Must be run by the CPU which is being attached.
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*/
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void
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cpu_setup(sc)
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struct cpu_softc *sc;
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{
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if (cpuinfo.hotfix)
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(*cpuinfo.hotfix)(&cpuinfo);
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/* Initialize FPU */
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fpu_init(&cpuinfo);
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/* Enable the cache */
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cpuinfo.cache_enable();
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cpu_hatched = 1;
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#if 0
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/* Flush cache line */
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cpuinfo.cache_flush((caddr_t)&cpu_hatched, sizeof(cpu_hatched));
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#endif
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}
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/*
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* Allocate per-CPU data, then start up this CPU using PROM.
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*/
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void
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cpu_spinup(sc)
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struct cpu_softc *sc;
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{
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#if defined(MULTIPROCESSOR)
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struct cpu_info *cpi = sc->sc_cpuinfo;
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int n;
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extern void cpu_hatch __P((void)); /* in locore.s */
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caddr_t pc = (caddr_t)cpu_hatch;
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struct openprom_addr oa;
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/* Setup CPU-specific MMU tables */
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pmap_alloc_cpu(cpi);
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cpu_hatched = 0;
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cpu_hatchstack = cpi->idle_u;
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cpu_hatch_sc = sc;
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/*
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* The physical address of the context table is passed to
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* the PROM in a "physical address descriptor".
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*/
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oa.oa_space = 0;
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oa.oa_base = (u_int32_t)cpi->ctx_tbl_pa;
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oa.oa_size = cpi->mmu_ncontext * sizeof(cpi->ctx_tbl[0]); /*???*/
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/*
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* Flush entire cache here, since the CPU may start with
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* caches off, hence no cache-coherency may be assumed.
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*/
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cpuinfo.cache_flush_all();
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prom_cpustart(cpi->node, &oa, 0, pc);
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/*
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* Wait for this CPU to spin up.
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*/
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for (n = 10000; n != 0; n--) {
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cpuinfo.cache_flush((caddr_t)&cpu_hatched, sizeof(cpu_hatched));
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if (cpu_hatched != 0) {
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return;
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}
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delay(100);
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}
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printf("CPU did not spin up\n");
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#endif
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}
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void
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mp_pause_cpus()
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{
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#if defined(MULTIPROCESSOR)
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int n;
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if (cpus == NULL)
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return;
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for (n = 0; n < ncpu; n++) {
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struct cpu_info *cpi = cpus[n];
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if (cpi == NULL || cpuinfo.mid == cpi->mid)
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continue;
|
|
simple_lock(&cpi->msg.lock);
|
|
cpi->msg.tag = XPMSG_PAUSECPU;
|
|
raise_ipi(cpi);
|
|
}
|
|
#endif
|
|
}
|
|
|
|
void
|
|
mp_resume_cpus()
|
|
{
|
|
#if defined(MULTIPROCESSOR)
|
|
int n;
|
|
|
|
if (cpus == NULL)
|
|
return;
|
|
|
|
for (n = 0; n < ncpu; n++) {
|
|
struct cpu_info *cpi = cpus[n];
|
|
if (cpi == NULL || cpuinfo.mid == cpi->mid)
|
|
continue;
|
|
|
|
simple_lock(&cpi->msg.lock);
|
|
cpi->msg.tag = XPMSG_RESUMECPU;
|
|
raise_ipi(cpi);
|
|
}
|
|
#endif
|
|
}
|
|
|
|
/*
|
|
* fpu_init() must be run on associated CPU.
|
|
*/
|
|
void
|
|
fpu_init(sc)
|
|
struct cpu_info *sc;
|
|
{
|
|
struct fpstate fpstate;
|
|
int fpuvers;
|
|
|
|
/*
|
|
* Get the FSR and clear any exceptions. If we do not unload
|
|
* the queue here and it is left over from a previous crash, we
|
|
* will panic in the first loadfpstate(), due to a sequence
|
|
* error, so we need to dump the whole state anyway.
|
|
*
|
|
* If there is no FPU, trap.c will advance over all the stores,
|
|
* so we initialize fs_fsr here.
|
|
*/
|
|
|
|
/* 7 is reserved for "none" */
|
|
fpstate.fs_fsr = 7 << FSR_VER_SHIFT;
|
|
savefpstate(&fpstate);
|
|
sc->fpuvers = fpuvers =
|
|
(fpstate.fs_fsr >> FSR_VER_SHIFT) & (FSR_VER >> FSR_VER_SHIFT);
|
|
|
|
if (fpuvers == 7) {
|
|
sc->fpu_name = "no";
|
|
return;
|
|
}
|
|
|
|
sc->fpupresent = 1;
|
|
sc->fpu_name = fsrtoname(sc->cpu_impl, sc->cpu_vers, fpuvers);
|
|
if (sc->fpu_name == NULL) {
|
|
sprintf(sc->fpu_namebuf, "version 0x%x", fpuvers);
|
|
sc->fpu_name = sc->fpu_namebuf;
|
|
}
|
|
}
|
|
|
|
void
|
|
cache_print(sc)
|
|
struct cpu_softc *sc;
|
|
{
|
|
struct cacheinfo *ci = &sc->sc_cpuinfo->cacheinfo;
|
|
|
|
printf("%s: ", sc->sc_dv.dv_xname);
|
|
|
|
if (ci->c_totalsize == 0) {
|
|
printf("no cache\n");
|
|
return;
|
|
}
|
|
|
|
if (ci->c_split) {
|
|
char *sep = "";
|
|
|
|
printf("%s", (ci->c_physical ? "physical " : ""));
|
|
if (ci->ic_totalsize > 0) {
|
|
printf("%s%dK instruction (%d b/l)", sep,
|
|
ci->ic_totalsize/1024, ci->ic_linesize);
|
|
sep = ", ";
|
|
}
|
|
if (ci->dc_totalsize > 0) {
|
|
printf("%s%dK data (%d b/l)", sep,
|
|
ci->dc_totalsize/1024, ci->dc_linesize);
|
|
}
|
|
} else if (ci->c_physical) {
|
|
/* combined, physical */
|
|
printf("physical %dK combined cache (%d bytes/line)",
|
|
ci->c_totalsize/1024, ci->c_linesize);
|
|
} else {
|
|
/* combined, virtual */
|
|
printf("%dK byte write-%s, %d bytes/line, %cw flush",
|
|
ci->c_totalsize/1024,
|
|
(ci->c_vactype == VAC_WRITETHROUGH) ? "through" : "back",
|
|
ci->c_linesize,
|
|
ci->c_hwflush ? 'h' : 's');
|
|
}
|
|
|
|
if (ci->ec_totalsize > 0) {
|
|
printf(", %dK external (%d b/l)",
|
|
ci->ec_totalsize/1024, ci->ec_linesize);
|
|
}
|
|
printf(": ");
|
|
if (ci->c_enabled)
|
|
printf("cache enabled");
|
|
printf("\n");
|
|
}
|
|
|
|
|
|
/*------------*/
|
|
|
|
|
|
void cpumatch_unknown __P((struct cpu_info *, struct module_info *, int));
|
|
void cpumatch_sun4 __P((struct cpu_info *, struct module_info *, int));
|
|
void cpumatch_sun4c __P((struct cpu_info *, struct module_info *, int));
|
|
void cpumatch_ms1 __P((struct cpu_info *, struct module_info *, int));
|
|
void cpumatch_viking __P((struct cpu_info *, struct module_info *, int));
|
|
void cpumatch_hypersparc __P((struct cpu_info *, struct module_info *, int));
|
|
void cpumatch_turbosparc __P((struct cpu_info *, struct module_info *, int));
|
|
|
|
void getcacheinfo_sun4 __P((struct cpu_info *, int node));
|
|
void getcacheinfo_sun4c __P((struct cpu_info *, int node));
|
|
void getcacheinfo_obp __P((struct cpu_info *, int node));
|
|
|
|
void sun4_hotfix __P((struct cpu_info *));
|
|
void viking_hotfix __P((struct cpu_info *));
|
|
void turbosparc_hotfix __P((struct cpu_info *));
|
|
void swift_hotfix __P((struct cpu_info *));
|
|
|
|
void ms1_mmu_enable __P((void));
|
|
void viking_mmu_enable __P((void));
|
|
void swift_mmu_enable __P((void));
|
|
void hypersparc_mmu_enable __P((void));
|
|
|
|
void srmmu_get_syncflt __P((void));
|
|
void ms1_get_syncflt __P((void));
|
|
void viking_get_syncflt __P((void));
|
|
void swift_get_syncflt __P((void));
|
|
void turbosparc_get_syncflt __P((void));
|
|
void hypersparc_get_syncflt __P((void));
|
|
void cypress_get_syncflt __P((void));
|
|
|
|
int srmmu_get_asyncflt __P((u_int *, u_int *));
|
|
int hypersparc_get_asyncflt __P((u_int *, u_int *));
|
|
int cypress_get_asyncflt __P((u_int *, u_int *));
|
|
int no_asyncflt_regs __P((u_int *, u_int *));
|
|
|
|
struct module_info module_unknown = {
|
|
CPUTYP_UNKNOWN,
|
|
VAC_UNKNOWN,
|
|
cpumatch_unknown
|
|
};
|
|
|
|
|
|
void
|
|
cpumatch_unknown(sc, mp, node)
|
|
struct cpu_info *sc;
|
|
struct module_info *mp;
|
|
int node;
|
|
{
|
|
panic("Unknown CPU type: "
|
|
"cpu: impl %d, vers %d; mmu: impl %d, vers %d",
|
|
sc->cpu_impl, sc->cpu_vers,
|
|
sc->mmu_impl, sc->mmu_vers);
|
|
}
|
|
|
|
#if defined(SUN4)
|
|
struct module_info module_sun4 = {
|
|
CPUTYP_UNKNOWN,
|
|
VAC_WRITETHROUGH,
|
|
cpumatch_sun4,
|
|
getcacheinfo_sun4,
|
|
sun4_hotfix,
|
|
0,
|
|
sun4_cache_enable,
|
|
0, /* ncontext set in `match' function */
|
|
0, /* get_syncflt(); unused in sun4c */
|
|
0, /* get_asyncflt(); unused in sun4c */
|
|
sun4_cache_flush,
|
|
sun4_vcache_flush_page,
|
|
sun4_vcache_flush_segment,
|
|
sun4_vcache_flush_region,
|
|
sun4_vcache_flush_context,
|
|
noop_pcache_flush_page,
|
|
noop_pure_vcache_flush,
|
|
noop_cache_flush_all,
|
|
0,
|
|
pmap_zero_page4_4c,
|
|
pmap_copy_page4_4c
|
|
};
|
|
|
|
void
|
|
getcacheinfo_sun4(sc, node)
|
|
struct cpu_info *sc;
|
|
int node;
|
|
{
|
|
struct cacheinfo *ci = &sc->cacheinfo;
|
|
|
|
switch (sc->cpu_type) {
|
|
case CPUTYP_4_100:
|
|
ci->c_vactype = VAC_NONE;
|
|
ci->c_totalsize = 0;
|
|
ci->c_hwflush = 0;
|
|
ci->c_linesize = 0;
|
|
ci->c_l2linesize = 0;
|
|
ci->c_split = 0;
|
|
ci->c_nlines = 0;
|
|
|
|
/* Override cache flush functions */
|
|
sc->sp_cache_flush = noop_cache_flush;
|
|
sc->sp_vcache_flush_page = noop_vcache_flush_page;
|
|
sc->sp_vcache_flush_segment = noop_vcache_flush_segment;
|
|
sc->sp_vcache_flush_region = noop_vcache_flush_region;
|
|
sc->sp_vcache_flush_context = noop_vcache_flush_context;
|
|
break;
|
|
case CPUTYP_4_200:
|
|
ci->c_vactype = VAC_WRITEBACK;
|
|
ci->c_totalsize = 128*1024;
|
|
ci->c_hwflush = 0;
|
|
ci->c_linesize = 16;
|
|
ci->c_l2linesize = 4;
|
|
ci->c_split = 0;
|
|
ci->c_nlines = ci->c_totalsize << ci->c_l2linesize;
|
|
break;
|
|
case CPUTYP_4_300:
|
|
ci->c_vactype = VAC_WRITEBACK;
|
|
ci->c_totalsize = 128*1024;
|
|
ci->c_hwflush = 0;
|
|
ci->c_linesize = 16;
|
|
ci->c_l2linesize = 4;
|
|
ci->c_split = 0;
|
|
ci->c_nlines = ci->c_totalsize << ci->c_l2linesize;
|
|
sc->flags |= CPUFLG_SUN4CACHEBUG;
|
|
break;
|
|
case CPUTYP_4_400:
|
|
ci->c_vactype = VAC_WRITEBACK;
|
|
ci->c_totalsize = 128 * 1024;
|
|
ci->c_hwflush = 0;
|
|
ci->c_linesize = 32;
|
|
ci->c_l2linesize = 5;
|
|
ci->c_split = 0;
|
|
ci->c_nlines = ci->c_totalsize << ci->c_l2linesize;
|
|
break;
|
|
}
|
|
}
|
|
|
|
struct idprom sun4_idprom_store;
|
|
void getidprom __P((struct idprom *, int size));
|
|
|
|
void
|
|
cpumatch_sun4(sc, mp, node)
|
|
struct cpu_info *sc;
|
|
struct module_info *mp;
|
|
int node;
|
|
{
|
|
extern struct idprom *idprom;
|
|
/*
|
|
* XXX - for e.g. myetheraddr(), which in sun4 can be called
|
|
* before the clock attaches.
|
|
*/
|
|
idprom = &sun4_idprom_store;
|
|
|
|
getidprom(&sun4_idprom_store, sizeof(struct idprom));
|
|
switch (sun4_idprom_store.id_machine) {
|
|
case ID_SUN4_100:
|
|
sc->cpu_type = CPUTYP_4_100;
|
|
sc->classlvl = 100;
|
|
sc->mmu_ncontext = 8;
|
|
sc->mmu_nsegment = 256;
|
|
/*XXX*/ sc->hz = 14280000;
|
|
break;
|
|
case ID_SUN4_200:
|
|
sc->cpu_type = CPUTYP_4_200;
|
|
sc->classlvl = 200;
|
|
sc->mmu_nsegment = 512;
|
|
sc->mmu_ncontext = 16;
|
|
/*XXX*/ sc->hz = 16670000;
|
|
break;
|
|
case ID_SUN4_300:
|
|
sc->cpu_type = CPUTYP_4_300;
|
|
sc->classlvl = 300;
|
|
sc->mmu_nsegment = 256;
|
|
sc->mmu_ncontext = 16;
|
|
/*XXX*/ sc->hz = 25000000;
|
|
break;
|
|
case ID_SUN4_400:
|
|
sc->cpu_type = CPUTYP_4_400;
|
|
sc->classlvl = 400;
|
|
sc->mmu_nsegment = 1024;
|
|
sc->mmu_ncontext = 64;
|
|
sc->mmu_nregion = 256;
|
|
/*XXX*/ sc->hz = 33000000;
|
|
sc->sun4_mmu3l = 1;
|
|
break;
|
|
}
|
|
|
|
}
|
|
#endif /* SUN4 */
|
|
|
|
#if defined(SUN4C)
|
|
struct module_info module_sun4c = {
|
|
CPUTYP_UNKNOWN,
|
|
VAC_WRITETHROUGH,
|
|
cpumatch_sun4c,
|
|
getcacheinfo_sun4c,
|
|
sun4_hotfix,
|
|
0,
|
|
sun4_cache_enable,
|
|
0, /* ncontext set in `match' function */
|
|
0, /* get_syncflt(); unused in sun4c */
|
|
0, /* get_asyncflt(); unused in sun4c */
|
|
sun4_cache_flush,
|
|
sun4_vcache_flush_page,
|
|
sun4_vcache_flush_segment,
|
|
sun4_vcache_flush_region,
|
|
sun4_vcache_flush_context,
|
|
noop_pcache_flush_page,
|
|
noop_pure_vcache_flush,
|
|
noop_cache_flush_all,
|
|
0,
|
|
pmap_zero_page4_4c,
|
|
pmap_copy_page4_4c
|
|
};
|
|
|
|
void
|
|
cpumatch_sun4c(sc, mp, node)
|
|
struct cpu_info *sc;
|
|
struct module_info *mp;
|
|
int node;
|
|
{
|
|
int rnode;
|
|
|
|
rnode = findroot();
|
|
sc->mmu_npmeg = sc->mmu_nsegment =
|
|
getpropint(rnode, "mmu-npmg", 128);
|
|
sc->mmu_ncontext = getpropint(rnode, "mmu-nctx", 8);
|
|
|
|
/* Get clock frequency */
|
|
sc->hz = getpropint(rnode, "clock-frequency", 0);
|
|
}
|
|
|
|
void
|
|
getcacheinfo_sun4c(sc, node)
|
|
struct cpu_info *sc;
|
|
int node;
|
|
{
|
|
struct cacheinfo *ci = &sc->cacheinfo;
|
|
int i, l;
|
|
|
|
if (node == 0)
|
|
/* Bootstrapping */
|
|
return;
|
|
|
|
/* Sun4c's have only virtually-addressed caches */
|
|
ci->c_physical = 0;
|
|
ci->c_totalsize = getpropint(node, "vac-size", 65536);
|
|
/*
|
|
* Note: vac-hwflush is spelled with an underscore
|
|
* on the 4/75s.
|
|
*/
|
|
ci->c_hwflush =
|
|
getpropint(node, "vac_hwflush", 0) |
|
|
getpropint(node, "vac-hwflush", 0);
|
|
|
|
ci->c_linesize = l = getpropint(node, "vac-linesize", 16);
|
|
for (i = 0; (1 << i) < l; i++)
|
|
/* void */;
|
|
if ((1 << i) != l)
|
|
panic("bad cache line size %d", l);
|
|
ci->c_l2linesize = i;
|
|
ci->c_associativity = 1;
|
|
ci->c_nlines = ci->c_totalsize << i;
|
|
|
|
ci->c_vactype = VAC_WRITETHROUGH;
|
|
|
|
/*
|
|
* Machines with "buserr-type" 1 have a bug in the cache
|
|
* chip that affects traps. (I wish I knew more about this
|
|
* mysterious buserr-type variable....)
|
|
*/
|
|
if (getpropint(node, "buserr-type", 0) == 1)
|
|
sc->flags |= CPUFLG_SUN4CACHEBUG;
|
|
}
|
|
#endif /* SUN4C */
|
|
|
|
void
|
|
sun4_hotfix(sc)
|
|
struct cpu_info *sc;
|
|
{
|
|
if ((sc->flags & CPUFLG_SUN4CACHEBUG) != 0) {
|
|
kvm_uncache((caddr_t)trapbase, 1);
|
|
printf(": cache chip bug; trap page uncached");
|
|
}
|
|
|
|
}
|
|
|
|
#if defined(SUN4M)
|
|
void
|
|
getcacheinfo_obp(sc, node)
|
|
struct cpu_info *sc;
|
|
int node;
|
|
{
|
|
struct cacheinfo *ci = &sc->cacheinfo;
|
|
int i, l;
|
|
|
|
if (node == 0)
|
|
/* Bootstrapping */
|
|
return;
|
|
|
|
/*
|
|
* Determine the Sun4m cache organization.
|
|
*/
|
|
ci->c_physical = node_has_property(node, "cache-physical?");
|
|
|
|
if (getpropint(node, "ncaches", 1) == 2)
|
|
ci->c_split = 1;
|
|
else
|
|
ci->c_split = 0;
|
|
|
|
/* hwflush is used only by sun4/4c code */
|
|
ci->c_hwflush = 0;
|
|
|
|
if (node_has_property(node, "icache-nlines") &&
|
|
node_has_property(node, "dcache-nlines") &&
|
|
ci->c_split) {
|
|
/* Harvard architecture: get I and D cache sizes */
|
|
ci->ic_nlines = getpropint(node, "icache-nlines", 0);
|
|
ci->ic_linesize = l =
|
|
getpropint(node, "icache-line-size", 0);
|
|
for (i = 0; (1 << i) < l && l; i++)
|
|
/* void */;
|
|
if ((1 << i) != l && l)
|
|
panic("bad icache line size %d", l);
|
|
ci->ic_l2linesize = i;
|
|
ci->ic_associativity =
|
|
getpropint(node, "icache-associativity", 1);
|
|
ci->ic_totalsize = l * ci->ic_nlines * ci->ic_associativity;
|
|
|
|
ci->dc_nlines = getpropint(node, "dcache-nlines", 0);
|
|
ci->dc_linesize = l =
|
|
getpropint(node, "dcache-line-size",0);
|
|
for (i = 0; (1 << i) < l && l; i++)
|
|
/* void */;
|
|
if ((1 << i) != l && l)
|
|
panic("bad dcache line size %d", l);
|
|
ci->dc_l2linesize = i;
|
|
ci->dc_associativity =
|
|
getpropint(node, "dcache-associativity", 1);
|
|
ci->dc_totalsize = l * ci->dc_nlines * ci->dc_associativity;
|
|
|
|
ci->c_l2linesize = min(ci->ic_l2linesize, ci->dc_l2linesize);
|
|
ci->c_linesize = min(ci->ic_linesize, ci->dc_linesize);
|
|
ci->c_totalsize = ci->ic_totalsize + ci->dc_totalsize;
|
|
} else {
|
|
/* unified I/D cache */
|
|
ci->c_nlines = getpropint(node, "cache-nlines", 128);
|
|
ci->c_linesize = l =
|
|
getpropint(node, "cache-line-size", 0);
|
|
for (i = 0; (1 << i) < l && l; i++)
|
|
/* void */;
|
|
if ((1 << i) != l && l)
|
|
panic("bad cache line size %d", l);
|
|
ci->c_l2linesize = i;
|
|
ci->c_totalsize = l *
|
|
ci->c_nlines *
|
|
getpropint(node, "cache-associativity", 1);
|
|
}
|
|
|
|
if (node_has_property(node, "ecache-nlines")) {
|
|
/* we have a L2 "e"xternal cache */
|
|
ci->ec_nlines = getpropint(node, "ecache-nlines", 32768);
|
|
ci->ec_linesize = l = getpropint(node, "ecache-line-size", 0);
|
|
for (i = 0; (1 << i) < l && l; i++)
|
|
/* void */;
|
|
if ((1 << i) != l && l)
|
|
panic("bad ecache line size %d", l);
|
|
ci->ec_l2linesize = i;
|
|
ci->ec_associativity =
|
|
getpropint(node, "ecache-associativity", 1);
|
|
ci->ec_totalsize = l * ci->ec_nlines * ci->ec_associativity;
|
|
}
|
|
if (ci->c_totalsize == 0)
|
|
printf("warning: couldn't identify cache\n");
|
|
}
|
|
|
|
/*
|
|
* We use the max. number of contexts on the micro and
|
|
* hyper SPARCs. The SuperSPARC would let us use up to 65536
|
|
* contexts (by powers of 2), but we keep it at 4096 since
|
|
* the table must be aligned to #context*4. With 4K contexts,
|
|
* we waste at most 16K of memory. Note that the context
|
|
* table is *always* page-aligned, so there can always be
|
|
* 1024 contexts without sacrificing memory space (given
|
|
* that the chip supports 1024 contexts).
|
|
*
|
|
* Currently known limits: MS1=64, MS2=256, HS=4096, SS=65536
|
|
* some old SS's=4096
|
|
*/
|
|
|
|
/* TI Microsparc I */
|
|
struct module_info module_ms1 = {
|
|
CPUTYP_MS1,
|
|
VAC_NONE,
|
|
cpumatch_ms1,
|
|
getcacheinfo_obp,
|
|
0,
|
|
ms1_mmu_enable,
|
|
ms1_cache_enable,
|
|
64,
|
|
ms1_get_syncflt,
|
|
no_asyncflt_regs,
|
|
ms1_cache_flush,
|
|
noop_vcache_flush_page,
|
|
noop_vcache_flush_segment,
|
|
noop_vcache_flush_region,
|
|
noop_vcache_flush_context,
|
|
noop_pcache_flush_page,
|
|
noop_pure_vcache_flush,
|
|
ms1_cache_flush_all,
|
|
memerr4m,
|
|
pmap_zero_page4m,
|
|
pmap_copy_page4m
|
|
};
|
|
|
|
void
|
|
cpumatch_ms1(sc, mp, node)
|
|
struct cpu_info *sc;
|
|
struct module_info *mp;
|
|
int node;
|
|
{
|
|
|
|
/*
|
|
* Turn off page zeroing in the idle loop; an unidentified
|
|
* bug causes (very sporadic) user process corruption.
|
|
*/
|
|
vm_page_zero_enable = 0;
|
|
}
|
|
|
|
void
|
|
ms1_mmu_enable()
|
|
{
|
|
}
|
|
|
|
/* TI Microsparc II */
|
|
struct module_info module_ms2 = { /* UNTESTED */
|
|
CPUTYP_MS2,
|
|
VAC_WRITETHROUGH,
|
|
0,
|
|
getcacheinfo_obp,
|
|
0,
|
|
0,
|
|
swift_cache_enable,
|
|
256,
|
|
srmmu_get_syncflt,
|
|
srmmu_get_asyncflt,
|
|
srmmu_cache_flush,
|
|
srmmu_vcache_flush_page,
|
|
srmmu_vcache_flush_segment,
|
|
srmmu_vcache_flush_region,
|
|
srmmu_vcache_flush_context,
|
|
noop_pcache_flush_page,
|
|
noop_pure_vcache_flush,
|
|
srmmu_cache_flush_all,
|
|
memerr4m,
|
|
pmap_zero_page4m,
|
|
pmap_copy_page4m
|
|
};
|
|
|
|
|
|
struct module_info module_swift = {
|
|
CPUTYP_MS2,
|
|
VAC_WRITETHROUGH,
|
|
0,
|
|
getcacheinfo_obp,
|
|
swift_hotfix,
|
|
0,
|
|
swift_cache_enable,
|
|
256,
|
|
swift_get_syncflt,
|
|
no_asyncflt_regs,
|
|
srmmu_cache_flush,
|
|
srmmu_vcache_flush_page,
|
|
srmmu_vcache_flush_segment,
|
|
srmmu_vcache_flush_region,
|
|
srmmu_vcache_flush_context,
|
|
noop_pcache_flush_page,
|
|
noop_pure_vcache_flush,
|
|
srmmu_cache_flush_all,
|
|
memerr4m,
|
|
pmap_zero_page4m,
|
|
pmap_copy_page4m
|
|
};
|
|
|
|
void
|
|
swift_hotfix(sc)
|
|
struct cpu_info *sc;
|
|
{
|
|
int pcr = lda(SRMMU_PCR, ASI_SRMMU);
|
|
|
|
/* Turn off branch prediction */
|
|
pcr &= ~SWIFT_PCR_BF;
|
|
sta(SRMMU_PCR, ASI_SRMMU, pcr);
|
|
}
|
|
|
|
void
|
|
swift_mmu_enable()
|
|
{
|
|
}
|
|
|
|
struct module_info module_viking = {
|
|
CPUTYP_UNKNOWN, /* set in cpumatch() */
|
|
VAC_NONE,
|
|
cpumatch_viking,
|
|
getcacheinfo_obp,
|
|
viking_hotfix,
|
|
viking_mmu_enable,
|
|
viking_cache_enable,
|
|
4096,
|
|
viking_get_syncflt,
|
|
no_asyncflt_regs,
|
|
/* supersparcs use cached DVMA, no need to flush */
|
|
noop_cache_flush,
|
|
noop_vcache_flush_page,
|
|
noop_vcache_flush_segment,
|
|
noop_vcache_flush_region,
|
|
noop_vcache_flush_context,
|
|
viking_pcache_flush_page,
|
|
noop_pure_vcache_flush,
|
|
noop_cache_flush_all,
|
|
viking_memerr,
|
|
pmap_zero_page4m,
|
|
pmap_copy_page4m
|
|
};
|
|
|
|
void
|
|
cpumatch_viking(sc, mp, node)
|
|
struct cpu_info *sc;
|
|
struct module_info *mp;
|
|
int node;
|
|
{
|
|
if (node == 0)
|
|
viking_hotfix(sc);
|
|
}
|
|
|
|
void
|
|
viking_hotfix(sc)
|
|
struct cpu_info *sc;
|
|
{
|
|
int pcr = lda(SRMMU_PCR, ASI_SRMMU);
|
|
|
|
/* Test if we're directly on the MBus */
|
|
if ((pcr & VIKING_PCR_MB) == 0) {
|
|
sc->mxcc = 1;
|
|
sc->flags |= CPUFLG_CACHE_MANDATORY;
|
|
sc->zero_page = pmap_zero_page_viking_mxcc;
|
|
sc->copy_page = pmap_copy_page_viking_mxcc;
|
|
/*
|
|
* Ok to cache PTEs; set the flag here, so we don't
|
|
* uncache in pmap_bootstrap().
|
|
*/
|
|
if ((pcr & VIKING_PCR_TC) == 0)
|
|
printf("[viking: PCR_TC is off]");
|
|
else
|
|
sc->flags |= CPUFLG_CACHEPAGETABLES;
|
|
} else {
|
|
sc->cache_flush = viking_cache_flush;
|
|
}
|
|
|
|
/* XXX! */
|
|
if (sc->mxcc)
|
|
sc->cpu_type = CPUTYP_SS1_MBUS_MXCC;
|
|
else
|
|
sc->cpu_type = CPUTYP_SS1_MBUS_NOMXCC;
|
|
}
|
|
|
|
void
|
|
viking_mmu_enable()
|
|
{
|
|
int pcr;
|
|
|
|
pcr = lda(SRMMU_PCR, ASI_SRMMU);
|
|
|
|
if (cpuinfo.mxcc) {
|
|
if ((pcr & VIKING_PCR_TC) == 0) {
|
|
printf("[viking: turn on PCR_TC]");
|
|
}
|
|
pcr |= VIKING_PCR_TC;
|
|
cpuinfo.flags |= CPUFLG_CACHEPAGETABLES;
|
|
} else
|
|
pcr &= ~VIKING_PCR_TC;
|
|
sta(SRMMU_PCR, ASI_SRMMU, pcr);
|
|
}
|
|
|
|
|
|
/* ROSS Hypersparc */
|
|
struct module_info module_hypersparc = {
|
|
CPUTYP_UNKNOWN,
|
|
VAC_WRITEBACK,
|
|
cpumatch_hypersparc,
|
|
getcacheinfo_obp,
|
|
0,
|
|
hypersparc_mmu_enable,
|
|
hypersparc_cache_enable,
|
|
4096,
|
|
hypersparc_get_syncflt,
|
|
hypersparc_get_asyncflt,
|
|
srmmu_cache_flush,
|
|
srmmu_vcache_flush_page,
|
|
srmmu_vcache_flush_segment,
|
|
srmmu_vcache_flush_region,
|
|
srmmu_vcache_flush_context,
|
|
noop_pcache_flush_page,
|
|
hypersparc_pure_vcache_flush,
|
|
hypersparc_cache_flush_all,
|
|
hypersparc_memerr,
|
|
pmap_zero_page4m,
|
|
pmap_copy_page4m
|
|
};
|
|
|
|
void
|
|
cpumatch_hypersparc(sc, mp, node)
|
|
struct cpu_info *sc;
|
|
struct module_info *mp;
|
|
int node;
|
|
{
|
|
sc->cpu_type = CPUTYP_HS_MBUS;/*XXX*/
|
|
if (node == 0)
|
|
sta(0, ASI_HICACHECLR, 0);
|
|
}
|
|
|
|
void
|
|
hypersparc_mmu_enable()
|
|
{
|
|
#if 0
|
|
int pcr;
|
|
|
|
pcr = lda(SRMMU_PCR, ASI_SRMMU);
|
|
pcr |= HYPERSPARC_PCR_C;
|
|
pcr &= ~HYPERSPARC_PCR_CE;
|
|
|
|
sta(SRMMU_PCR, ASI_SRMMU, pcr);
|
|
#endif
|
|
}
|
|
|
|
/* Cypress 605 */
|
|
struct module_info module_cypress = {
|
|
CPUTYP_CYPRESS,
|
|
VAC_WRITEBACK,
|
|
0,
|
|
getcacheinfo_obp,
|
|
0,
|
|
0,
|
|
cypress_cache_enable,
|
|
4096,
|
|
cypress_get_syncflt,
|
|
cypress_get_asyncflt,
|
|
srmmu_cache_flush,
|
|
srmmu_vcache_flush_page,
|
|
srmmu_vcache_flush_segment,
|
|
srmmu_vcache_flush_region,
|
|
srmmu_vcache_flush_context,
|
|
noop_pcache_flush_page,
|
|
noop_pure_vcache_flush,
|
|
cypress_cache_flush_all,
|
|
memerr4m,
|
|
pmap_zero_page4m,
|
|
pmap_copy_page4m
|
|
};
|
|
|
|
/* Fujitsu Turbosparc */
|
|
struct module_info module_turbosparc = {
|
|
CPUTYP_MS2,
|
|
VAC_WRITEBACK,
|
|
cpumatch_turbosparc,
|
|
getcacheinfo_obp,
|
|
turbosparc_hotfix,
|
|
0,
|
|
turbosparc_cache_enable,
|
|
256,
|
|
turbosparc_get_syncflt,
|
|
no_asyncflt_regs,
|
|
srmmu_cache_flush,
|
|
srmmu_vcache_flush_page,
|
|
srmmu_vcache_flush_segment,
|
|
srmmu_vcache_flush_region,
|
|
srmmu_vcache_flush_context,
|
|
noop_pcache_flush_page,
|
|
noop_pure_vcache_flush,
|
|
srmmu_cache_flush_all,
|
|
memerr4m,
|
|
pmap_zero_page4m,
|
|
pmap_copy_page4m
|
|
};
|
|
|
|
void
|
|
cpumatch_turbosparc(sc, mp, node)
|
|
struct cpu_info *sc;
|
|
struct module_info *mp;
|
|
int node;
|
|
{
|
|
int i;
|
|
|
|
if (node == 0 || sc->master == 0)
|
|
return;
|
|
|
|
i = getpsr();
|
|
if (sc->cpu_vers == IU_VERS(i))
|
|
return;
|
|
|
|
/*
|
|
* A cloaked Turbosparc: clear any items in cpuinfo that
|
|
* might have been set to uS2 versions during bootstrap.
|
|
*/
|
|
sc->cpu_name = 0;
|
|
sc->mmu_ncontext = 0;
|
|
sc->cpu_type = 0;
|
|
sc->cacheinfo.c_vactype = 0;
|
|
sc->hotfix = 0;
|
|
sc->mmu_enable = 0;
|
|
sc->cache_enable = 0;
|
|
sc->get_syncflt = 0;
|
|
sc->sp_cache_flush = 0;
|
|
sc->sp_vcache_flush_page = 0;
|
|
sc->sp_vcache_flush_segment = 0;
|
|
sc->sp_vcache_flush_region = 0;
|
|
sc->sp_vcache_flush_context = 0;
|
|
sc->pcache_flush_page = 0;
|
|
}
|
|
|
|
void
|
|
turbosparc_hotfix(sc)
|
|
struct cpu_info *sc;
|
|
{
|
|
int pcf;
|
|
|
|
pcf = lda(SRMMU_PCFG, ASI_SRMMU);
|
|
if (pcf & TURBOSPARC_PCFG_US2) {
|
|
/* Turn off uS2 emulation bit */
|
|
pcf &= ~TURBOSPARC_PCFG_US2;
|
|
sta(SRMMU_PCFG, ASI_SRMMU, pcf);
|
|
}
|
|
}
|
|
#endif /* SUN4M */
|
|
|
|
|
|
#define ANY -1 /* match any version */
|
|
|
|
struct cpu_conf {
|
|
int arch;
|
|
int cpu_impl;
|
|
int cpu_vers;
|
|
int mmu_impl;
|
|
int mmu_vers;
|
|
char *name;
|
|
struct module_info *minfo;
|
|
} cpu_conf[] = {
|
|
#if defined(SUN4)
|
|
{ CPU_SUN4, 0, 0, ANY, ANY, "MB86900/1A or L64801", &module_sun4 },
|
|
{ CPU_SUN4, 1, 0, ANY, ANY, "L64811", &module_sun4 },
|
|
{ CPU_SUN4, 1, 1, ANY, ANY, "CY7C601", &module_sun4 },
|
|
#endif
|
|
|
|
#if defined(SUN4C)
|
|
{ CPU_SUN4C, 0, 0, ANY, ANY, "MB86900/1A or L64801", &module_sun4c },
|
|
{ CPU_SUN4C, 1, 0, ANY, ANY, "L64811", &module_sun4c },
|
|
{ CPU_SUN4C, 1, 1, ANY, ANY, "CY7C601", &module_sun4c },
|
|
{ CPU_SUN4C, 9, 0, ANY, ANY, "W8601/8701 or MB86903", &module_sun4c },
|
|
#endif
|
|
|
|
#if defined(SUN4M)
|
|
{ CPU_SUN4M, 0, 4, 0, 4, "MB86904", &module_swift },
|
|
{ CPU_SUN4M, 0, 5, 0, 5, "MB86907", &module_turbosparc },
|
|
{ CPU_SUN4M, 1, 1, 1, 0, "CY7C601/604", &module_cypress },
|
|
{ CPU_SUN4M, 1, 1, 1, 0xb, "CY7C601/605 (v.b)", &module_cypress },
|
|
{ CPU_SUN4M, 1, 1, 1, 0xc, "CY7C601/605 (v.c)", &module_cypress },
|
|
{ CPU_SUN4M, 1, 1, 1, 0xf, "CY7C601/605 (v.f)", &module_cypress },
|
|
{ CPU_SUN4M, 1, 3, 1, ANY, "CY7C611", &module_cypress },
|
|
{ CPU_SUN4M, 1, 0xe, 1, 7, "RT620/625", &module_hypersparc },
|
|
{ CPU_SUN4M, 1, 0xf, 1, 7, "RT620/625", &module_hypersparc },
|
|
{ CPU_SUN4M, 4, 0, 0, ANY, "TMS390Z50 v0 or TMS390Z55", &module_viking },
|
|
{ CPU_SUN4M, 4, 1, 0, ANY, "TMS390Z50 v1", &module_viking },
|
|
{ CPU_SUN4M, 4, 1, 4, ANY, "TMS390S10", &module_ms1 },
|
|
{ CPU_SUN4M, 4, 2, 0, ANY, "TI_MS2", &module_ms2 },
|
|
{ CPU_SUN4M, 4, 3, ANY, ANY, "TI_4_3", &module_viking },
|
|
{ CPU_SUN4M, 4, 4, ANY, ANY, "TI_4_4", &module_viking },
|
|
#endif
|
|
|
|
{ ANY, ANY, ANY, ANY, ANY, "Unknown", &module_unknown }
|
|
};
|
|
|
|
void
|
|
getcpuinfo(sc, node)
|
|
struct cpu_info *sc;
|
|
int node;
|
|
{
|
|
struct cpu_conf *mp;
|
|
int i;
|
|
int cpu_impl, cpu_vers;
|
|
int mmu_impl, mmu_vers;
|
|
|
|
/*
|
|
* Set up main criteria for selection from the CPU configuration
|
|
* table: the CPU implementation/version fields from the PSR
|
|
* register, and -- on sun4m machines -- the MMU
|
|
* implementation/version from the SCR register.
|
|
*/
|
|
if (sc->master) {
|
|
i = getpsr();
|
|
if (node == 0 ||
|
|
(cpu_impl =
|
|
getpropint(node, "psr-implementation", -1)) == -1)
|
|
cpu_impl = IU_IMPL(i);
|
|
|
|
if (node == 0 ||
|
|
(cpu_vers = getpropint(node, "psr-version", -1)) == -1)
|
|
cpu_vers = IU_VERS(i);
|
|
|
|
if (CPU_ISSUN4M) {
|
|
i = lda(SRMMU_PCR, ASI_SRMMU);
|
|
if (node == 0 ||
|
|
(mmu_impl =
|
|
getpropint(node, "implementation", -1)) == -1)
|
|
mmu_impl = SRMMU_IMPL(i);
|
|
|
|
if (node == 0 ||
|
|
(mmu_vers = getpropint(node, "version", -1)) == -1)
|
|
mmu_vers = SRMMU_VERS(i);
|
|
} else {
|
|
mmu_impl = ANY;
|
|
mmu_vers = ANY;
|
|
}
|
|
} else {
|
|
/*
|
|
* Get CPU version/implementation from ROM. If not
|
|
* available, assume same as boot CPU.
|
|
*/
|
|
cpu_impl = getpropint(node, "psr-implementation", -1);
|
|
if (cpu_impl == -1)
|
|
cpu_impl = cpuinfo.cpu_impl;
|
|
cpu_vers = getpropint(node, "psr-version", -1);
|
|
if (cpu_vers == -1)
|
|
cpu_vers = cpuinfo.cpu_vers;
|
|
|
|
/* Get MMU version/implementation from ROM always */
|
|
mmu_impl = getpropint(node, "implementation", -1);
|
|
mmu_vers = getpropint(node, "version", -1);
|
|
}
|
|
|
|
for (mp = cpu_conf; ; mp++) {
|
|
if (mp->arch != cputyp && mp->arch != ANY)
|
|
continue;
|
|
|
|
#define MATCH(x) (mp->x == x || mp->x == ANY)
|
|
if (!MATCH(cpu_impl) ||
|
|
!MATCH(cpu_vers) ||
|
|
!MATCH(mmu_impl) ||
|
|
!MATCH(mmu_vers))
|
|
continue;
|
|
#undef MATCH
|
|
|
|
/*
|
|
* Got CPU type.
|
|
*/
|
|
sc->cpu_impl = cpu_impl;
|
|
sc->cpu_vers = cpu_vers;
|
|
sc->mmu_impl = mmu_impl;
|
|
sc->mmu_vers = mmu_vers;
|
|
|
|
if (mp->minfo->cpu_match) {
|
|
/* Additional fixups */
|
|
mp->minfo->cpu_match(sc, mp->minfo, node);
|
|
}
|
|
if (sc->cpu_name == 0)
|
|
sc->cpu_name = mp->name;
|
|
|
|
if (sc->mmu_ncontext == 0)
|
|
sc->mmu_ncontext = mp->minfo->ncontext;
|
|
|
|
if (sc->cpu_type == 0)
|
|
sc->cpu_type = mp->minfo->cpu_type;
|
|
|
|
if (sc->cacheinfo.c_vactype == VAC_UNKNOWN)
|
|
sc->cacheinfo.c_vactype = mp->minfo->vactype;
|
|
|
|
mp->minfo->getcacheinfo(sc, node);
|
|
|
|
if (node && sc->hz == 0 && !CPU_ISSUN4/*XXX*/) {
|
|
sc->hz = getpropint(node, "clock-frequency", 0);
|
|
if (sc->hz == 0) {
|
|
/*
|
|
* Try to find it in the OpenPROM root...
|
|
*/
|
|
sc->hz = getpropint(findroot(),
|
|
"clock-frequency", 0);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Copy CPU/MMU/Cache specific routines into cpu_info.
|
|
*/
|
|
#define MPCOPY(x) if (sc->x == 0) sc->x = mp->minfo->x;
|
|
MPCOPY(hotfix);
|
|
MPCOPY(mmu_enable);
|
|
MPCOPY(cache_enable);
|
|
MPCOPY(get_syncflt);
|
|
MPCOPY(get_asyncflt);
|
|
MPCOPY(sp_cache_flush);
|
|
MPCOPY(sp_vcache_flush_page);
|
|
MPCOPY(sp_vcache_flush_segment);
|
|
MPCOPY(sp_vcache_flush_region);
|
|
MPCOPY(sp_vcache_flush_context);
|
|
MPCOPY(pcache_flush_page);
|
|
MPCOPY(pure_vcache_flush);
|
|
MPCOPY(cache_flush_all);
|
|
MPCOPY(memerr);
|
|
MPCOPY(zero_page);
|
|
MPCOPY(copy_page);
|
|
#undef MPCOPY
|
|
/*
|
|
* Use the single-processor cache flush functions until
|
|
* all CPUs are initialized.
|
|
*/
|
|
sc->cache_flush = sc->sp_cache_flush;
|
|
sc->vcache_flush_page = sc->sp_vcache_flush_page;
|
|
sc->vcache_flush_segment = sc->sp_vcache_flush_segment;
|
|
sc->vcache_flush_region = sc->sp_vcache_flush_region;
|
|
sc->vcache_flush_context = sc->sp_vcache_flush_context;
|
|
return;
|
|
}
|
|
panic("Out of CPUs");
|
|
}
|
|
|
|
/*
|
|
* The following tables convert <IU impl, IU version, FPU version> triples
|
|
* into names for the CPU and FPU chip. In most cases we do not need to
|
|
* inspect the FPU version to name the IU chip, but there is one exception
|
|
* (for Tsunami), and this makes the tables the same.
|
|
*
|
|
* The table contents (and much of the structure here) are from Guy Harris.
|
|
*
|
|
*/
|
|
struct info {
|
|
int valid;
|
|
int iu_impl;
|
|
int iu_vers;
|
|
int fpu_vers;
|
|
char *name;
|
|
};
|
|
|
|
/* NB: table order matters here; specific numbers must appear before ANY. */
|
|
static struct info fpu_types[] = {
|
|
/*
|
|
* Vendor 0, IU Fujitsu0.
|
|
*/
|
|
{ 1, 0x0, ANY, 0, "MB86910 or WTL1164/5" },
|
|
{ 1, 0x0, ANY, 1, "MB86911 or WTL1164/5" },
|
|
{ 1, 0x0, ANY, 2, "L64802 or ACT8847" },
|
|
{ 1, 0x0, ANY, 3, "WTL3170/2" },
|
|
{ 1, 0x0, 4, 4, "on-chip" }, /* Swift */
|
|
{ 1, 0x0, 5, 5, "on-chip" }, /* TurboSparc */
|
|
{ 1, 0x0, ANY, 4, "L64804" },
|
|
|
|
/*
|
|
* Vendor 1, IU ROSS0/1 or Pinnacle.
|
|
*/
|
|
{ 1, 0x1, 0xf, 0, "on-chip" }, /* Pinnacle */
|
|
{ 1, 0x1, 0xe, 0, "on-chip" }, /* Hypersparc RT 625/626 */
|
|
{ 1, 0x1, ANY, 0, "L64812 or ACT8847" },
|
|
{ 1, 0x1, ANY, 1, "L64814" },
|
|
{ 1, 0x1, ANY, 2, "TMS390C602A" },
|
|
{ 1, 0x1, ANY, 3, "RT602 or WTL3171" },
|
|
|
|
/*
|
|
* Vendor 2, IU BIT0.
|
|
*/
|
|
{ 1, 0x2, ANY, 0, "B5010 or B5110/20 or B5210" },
|
|
|
|
/*
|
|
* Vendor 4, Texas Instruments.
|
|
*/
|
|
{ 1, 0x4, ANY, 0, "on-chip" }, /* Viking */
|
|
{ 1, 0x4, ANY, 4, "on-chip" }, /* Tsunami */
|
|
|
|
/*
|
|
* Vendor 5, IU Matsushita0.
|
|
*/
|
|
{ 1, 0x5, ANY, 0, "on-chip" },
|
|
|
|
/*
|
|
* Vendor 9, Weitek.
|
|
*/
|
|
{ 1, 0x9, ANY, 3, "on-chip" },
|
|
|
|
{ 0 }
|
|
};
|
|
|
|
static char *
|
|
fsrtoname(impl, vers, fver)
|
|
int impl, vers, fver;
|
|
{
|
|
struct info *p;
|
|
|
|
for (p = fpu_types; p->valid; p++) {
|
|
if (p->iu_impl == impl &&
|
|
(p->iu_vers == vers || p->iu_vers == ANY) &&
|
|
(p->fpu_vers == fver))
|
|
return (p->name);
|
|
}
|
|
return (NULL);
|
|
}
|
|
|
|
#ifdef DDB
|
|
|
|
#include <ddb/db_output.h>
|
|
#include <machine/db_machdep.h>
|
|
|
|
#include "ioconf.h"
|
|
|
|
void cpu_debug_dump(void);
|
|
|
|
/*
|
|
* Dump cpu information from ddb.
|
|
*/
|
|
void
|
|
cpu_debug_dump(void)
|
|
{
|
|
struct cpu_info *ci;
|
|
CPU_INFO_ITERATOR cii;
|
|
|
|
db_printf("addr cpuid flags curproc fpproc\n");
|
|
for (CPU_INFO_FOREACH(cii, ci)) {
|
|
db_printf("%p %d %x %10p %10p\n",
|
|
ci,
|
|
ci->ci_cpuid,
|
|
ci->flags,
|
|
ci->ci_curproc,
|
|
ci->fpproc);
|
|
}
|
|
}
|
|
#endif
|