258 lines
6.6 KiB
C
258 lines
6.6 KiB
C
/* $NetBSD: plumiobus.c,v 1.2 1999/12/07 17:37:21 uch Exp $ */
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/*
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* Copyright (c) 1999, by UCHIYAMA Yasushi
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. The name of the developer may NOT be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#include "opt_tx39_debug.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <sys/malloc.h>
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <hpcmips/tx/tx39var.h>
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#include <hpcmips/dev/plumvar.h>
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#include <hpcmips/dev/plumicuvar.h>
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#include <hpcmips/dev/plumpowervar.h>
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#include <hpcmips/dev/plumiobusreg.h>
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#include <hpcmips/dev/plumiobusvar.h>
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#include "locators.h"
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int plumiobus_match __P((struct device*, struct cfdata*, void*));
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void plumiobus_attach __P((struct device*, struct device*, void*));
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int plumiobus_print __P((void*, const char*));
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int plumiobus_search __P((struct device*, struct cfdata*, void*));
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struct plumisa_resource {
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int pr_irq;
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bus_space_tag_t pr_iot;
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int pr_enabled;
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};
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struct plumiobus_softc {
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struct device sc_dev;
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plum_chipset_tag_t sc_pc;
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bus_space_tag_t sc_regt;
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bus_space_handle_t sc_regh;
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bus_space_tag_t sc_iot;
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bus_space_handle_t sc_ioh;
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struct plumisa_resource sc_isa[PLUM_IOBUS_IO5CSMAX];
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};
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struct cfattach plumiobus_ca = {
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sizeof(struct plumiobus_softc), plumiobus_match, plumiobus_attach
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};
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void plumiobus_dump __P((struct plumiobus_softc*));
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bus_space_tag_t __plumiobus_subregion __P((bus_space_tag_t, bus_addr_t, bus_size_t));
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int
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plumiobus_match(parent, cf, aux)
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struct device *parent;
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struct cfdata *cf;
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void *aux;
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{
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return 1;
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}
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void
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plumiobus_attach(parent, self, aux)
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struct device *parent;
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struct device *self;
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void *aux;
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{
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struct plum_attach_args *pa = aux;
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struct plumiobus_softc *sc = (void*)self;
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struct plumisa_resource *pr;
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sc->sc_pc = pa->pa_pc;
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sc->sc_regt = pa->pa_regt;
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sc->sc_iot = pa->pa_iot;
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if (bus_space_map(sc->sc_regt, PLUM_IOBUS_REGBASE,
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PLUM_IOBUS_REGSIZE, 0, &sc->sc_regh)) {
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printf(": register map failed.\n");
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return;
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}
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printf("\n");
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plum_power_establish(sc->sc_pc, PLUM_PWR_IO5);
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/* Address space <-> IRQ mapping */
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pr = &sc->sc_isa[IO5CS0];
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pr->pr_irq = PLUM_INT_EXT5IO0;
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pr->pr_iot = __plumiobus_subregion(
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sc->sc_iot,
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PLUM_IOBUS_IOBASE + PLUM_IOBUS_IO5CS0BASE,
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PLUM_IOBUS_IO5SIZE);
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pr = &sc->sc_isa[IO5CS1];
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pr->pr_irq = PLUM_INT_EXT5IO1;
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pr->pr_iot = __plumiobus_subregion(
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sc->sc_iot,
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PLUM_IOBUS_IOBASE + PLUM_IOBUS_IO5CS1BASE,
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PLUM_IOBUS_IO5SIZE);
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pr = &sc->sc_isa[IO5CS2];
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pr->pr_irq = PLUM_INT_EXT5IO2;
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pr->pr_iot = __plumiobus_subregion(
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sc->sc_iot,
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PLUM_IOBUS_IOBASE + PLUM_IOBUS_IO5CS2BASE,
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PLUM_IOBUS_IO5SIZE);
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pr = &sc->sc_isa[IO5CS3];
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pr->pr_irq = PLUM_INT_EXT5IO3;
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pr->pr_iot = __plumiobus_subregion(
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sc->sc_iot,
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PLUM_IOBUS_IOBASE + PLUM_IOBUS_IO5CS3BASE,
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PLUM_IOBUS_IO5SIZE);
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pr = &sc->sc_isa[IO5CS4];
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pr->pr_irq = PLUM_INT_EXT3IO0; /* XXX */
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pr->pr_iot = __plumiobus_subregion(
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sc->sc_iot,
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PLUM_IOBUS_IOBASE + PLUM_IOBUS_IO5CS4BASE,
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PLUM_IOBUS_IO5SIZE);
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pr = &sc->sc_isa[IO5NCS];
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pr->pr_irq = PLUM_INT_EXT3IO1;
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pr->pr_iot = __plumiobus_subregion(
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sc->sc_iot,
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PLUM_IOBUS_IOBASE + PLUM_IOBUS_IO5CS5BASE,
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PLUM_IOBUS_IO5SIZE);
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plumiobus_dump(sc);
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config_search(plumiobus_search, self, plumiobus_print);
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}
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/* XXX something kludge */
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bus_space_tag_t
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__plumiobus_subregion(t, ofs, size)
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bus_space_tag_t t;
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bus_addr_t ofs;
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bus_size_t size;
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{
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struct hpcmips_bus_space *hbs;
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if (!(hbs = malloc(sizeof(struct hpcmips_bus_space),
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M_DEVBUF, M_NOWAIT))) {
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panic ("__plumiobus_subregion: no memory.");
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}
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*hbs = *t;
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hbs->t_base += ofs;
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hbs->t_size = size;
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return hbs;
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}
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int
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plumiobus_search(parent, cf, aux)
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struct device *parent;
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struct cfdata *cf;
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void *aux;
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{
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struct plumiobus_softc *sc = (void*)parent;
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struct plumiobus_attach_args pba;
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int slot;
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/* Disallow wildcarded IO5CS slot */
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if (cf->cf_loc[PLUMIOBUSIFCF_SLOT] == PLUMIOBUSIFCF_SLOT_DEFAULT) {
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printf("plumiobus_search: wildcarded slot, skipping\n");
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return 0;
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}
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slot = pba.pba_slot = cf->cf_loc[PLUMIOBUSIFCF_SLOT];
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pba.pba_pc = sc->sc_pc;
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pba.pba_iot = sc->sc_isa[slot].pr_iot;
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pba.pba_irq = sc->sc_isa[slot].pr_irq;
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pba.pba_busname = "plumisab";
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if (!(sc->sc_isa[slot].pr_enabled) && /* not attached slot */
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(*cf->cf_attach->ca_match)(parent, cf, &pba)) {
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config_attach(parent, cf, &pba, plumiobus_print);
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sc->sc_isa[slot].pr_enabled = 1;
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}
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return 0;
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}
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int
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plumiobus_print(aux, pnp)
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void *aux;
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const char *pnp;
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{
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return pnp ? QUIET : UNCONF;
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}
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void
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plumiobus_dump(sc)
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struct plumiobus_softc *sc;
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{
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bus_space_tag_t regt = sc->sc_regt;
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bus_space_handle_t regh = sc->sc_regh;
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plumreg_t reg;
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int i, wait;
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reg = plum_conf_read(regt, regh, PLUM_IOBUS_IOXBSZ_REG);
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printf("8bit port:");
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for (i = 0; i < 6; i++) {
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if (reg & (1 << i)) {
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printf(" IO5CS%d", i);
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}
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}
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printf("\n");
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reg = PLUM_IOBUS_IOXCCNT_MASK &
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plum_conf_read(regt, regh, PLUM_IOBUS_IOXCCNT_REG);
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printf(" # of wait to become from the access begining: %d clock\n",
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reg + 1);
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reg = plum_conf_read(regt, regh, PLUM_IOBUS_IOXACNT_REG);
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printf(" # of wait in access clock: ");
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for (i = 0; i < 5; i++) {
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wait = (reg >> (i * PLUM_IOBUS_IOXACNT_SHIFT))
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& PLUM_IOBUS_IOXACNT_MASK;
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printf("[CS%d:%d] ", i, wait + 1);
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}
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printf("\n");
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reg = PLUM_IOBUS_IOXSCNT_MASK &
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plum_conf_read(regt, regh, PLUM_IOBUS_IOXSCNT_REG);
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printf(" # of wait during access by I/O bus : %d clock\n", reg + 1);
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reg = plum_conf_read(regt, regh, PLUM_IOBUS_IDEMODE_REG);
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if (reg & PLUM_IOBUS_IDEMODE) {
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printf("IO5CS3,4 IDE mode\n");
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}
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}
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