NetBSD/sys/arch/alpha/include/atomic.h

/* $NetBSD: atomic.h,v 1.2 1999/12/03 01:13:17 thorpej Exp $ */

/*-
 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc.
 * All rights reserved.
 *
 * This code is derived from software contributed to The NetBSD Foundation
 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
 * NASA Ames Research Center.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. All advertising materials mentioning features or use of this software
 *    must display the following acknowledgement:
 *	This product includes software developed by the NetBSD
 *	Foundation, Inc. and its contributors.
 * 4. Neither the name of The NetBSD Foundation nor the names of its
 *    contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 * POSSIBILITY OF SUCH DAMAGE.
 */

/*
 * Misc. `atomic' operations.
 */

#ifndef _ALPHA_ATOMIC_H_
#define	_ALPHA_ATOMIC_H_

static __inline void alpha_atomic_setbits_q __P((__volatile unsigned long *,
	unsigned long)) __attribute__((__unused__));
static __inline void alpha_atomic_clearbits_q __P((__volatile unsigned long *,
	unsigned long)) __attribute__((__unused__));

static __inline void alpha_atomic_add_q __P((__volatile unsigned long *,
	unsigned long)) __attribute__((__unused__));
static __inline void alpha_atomic_sub_q __P((__volatile unsigned long *,
	unsigned long)) __attribute__((__unused__));

static __inline unsigned long alpha_atomic_loadlatch_q
	__P((__volatile unsigned long *, unsigned long))
	__attribute__((__unused__));

/*
 * alpha_atomic_setbits_q:
 *
 *	Atomically set bits in a quadword.
 */
static __inline void
alpha_atomic_setbits_q(ulp, v)
	__volatile unsigned long *ulp;
	unsigned long v;
{
	unsigned long t0;

	__asm __volatile(
		"# BEGIN alpha_atomic_setbits_q\n"
		"1:	ldq_l	%0, %3		\n"
		"	or	%0, %2, %0	\n"
		"	stq_c	%0, %1		\n"
		"	beq	%0, 2f		\n"
		"	mb			\n"
		"	br	3f		\n"
		"2:	br	1b		\n"
		"3:				\n"
		"	# END alpha_atomic_setbits_q"
		: "=r" (t0), "=m" (*ulp)
		: "r" (v), "1" (*ulp));
}

/*
 * alpha_atomic_clearbits_q:
 *
 *	Atomically clear bits in a quadword.
 */
static __inline void
alpha_atomic_clearbits_q(ulp, v)
	__volatile unsigned long *ulp;
	unsigned long v;
{
	unsigned long t0;

	__asm __volatile(
		"# BEGIN alpha_atomic_clearbits_q\n"
		"1:	ldq_l	%0, %3		\n"
		"	and	%0, %2, %0	\n"
		"	stq_c	%0, %1		\n"
		"	beq	%0, 2f		\n"
		"	mb			\n"
		"	br	3f		\n"
		"2:	br	1b		\n"
		"3:				\n"
		"	# END alpha_atomic_clearbits_q"
		: "=r" (t0), "=m" (*ulp)
		: "r" (~v), "1" (*ulp));
}

/*
 * alpha_atomic_add_q:
 *
 *	Atomically add a value to a quadword.
 */
static __inline void
alpha_atomic_add_q(ulp, v)
	__volatile unsigned long *ulp;
	unsigned long v;
{
	unsigned long t0;

	__asm __volatile(
		"# BEGIN alpha_atomic_add_q\n"
		"1:	ldq_l	%0, %3		\n"
		"	addq	%0, %2, %0	\n"
		"	stq_c	%0, %1		\n"
		"	beq	%0, 2f		\n"
		"	mb			\n"
		"	br	3f		\n"
		"2:	br	1b		\n"
		"3:				\n"
		"	# END alpha_atomic_add_q"
		: "=r" (t0), "=m" (*ulp)
		: "r" (v), "1" (*ulp));
}

/*
 * alpha_atomic_sub_q:
 *
 *	Atomically subtract a value from a quadword.
 */
static __inline void
alpha_atomic_sub_q(ulp, v)
	__volatile unsigned long *ulp;
	unsigned long v;
{
	unsigned long t0;

	__asm __volatile(
		"# BEGIN alpha_atomic_sub_q\n"
		"1:	ldq_l	%0, %3		\n"
		"	subq	%0, %2, %0	\n"
		"	stq_c	%0, %1		\n"
		"	beq	%0, 2f		\n"
		"	mb			\n"
		"	br	3f		\n"
		"2:	br	1b		\n"
		"3:				\n"
		"	# END alpha_atomic_sub_q"
		: "=r" (t0), "=m" (*ulp)
		: "r" (v), "1" (*ulp));
}

/*
 * alpha_atomic_loadlatch_q:
 *
 *	Atomically load and latch a quadword value.
 */
static __inline unsigned long
alpha_atomic_loadlatch_q(ulp, v)
	__volatile unsigned long *ulp;
	unsigned long v;
{
	unsigned long t0, v0;

	__asm __volatile(
		"# BEGIN alpha_atomic_loadlatch_q\n"
		"1:	mov	%3, %0		\n"
		"	ldq_l	%1, %4		\n"
		"	stq_c	%0, %2		\n"
		"	beq	%0, 2f		\n"
		"	mb			\n"
		"	br	3f		\n"
		"2:	br	1b		\n"
		"3:				\n"
		"	# END alpha_atomic_loadlatch_q"
		: "=r" (t0), "=r" (v0), "=m" (*ulp)
		: "r" (v), "2" (*ulp));

	return (v0);
}

#endif /* _ALPHA_ATOMIC_H_ */