51 lines
1.3 KiB
C
51 lines
1.3 KiB
C
/* $NetBSD: gemini_ipmvar.h,v 1.1 2008/12/06 05:22:39 cliff Exp $ */
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#ifndef _GEMINI_IPMVAR_H_
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#define _GEMINI_IPMVAR_H_
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/*
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* message queue
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*
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* - the queue gets located in memory shared between cores
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* - is mapped non-cached so SW coherency is not required.
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* - be sure ipm_queue_t starts on 32 bit (min) boundary to align descriptors
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* - note that indicies are 8 bit and NIPMDESC < (1<<8)
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* be sure to adjust typedef if size is increased
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* - current sizes, typedef, and padding make sizeof(ipm_queue_t) == 4096
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*/
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typedef uint32_t ipmqindex_t;
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#define NIPMDESC 255
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#define IPMQPADSZ (4096 - ((sizeof(ipm_desc_t) * NIPMDESC) + (2 * sizeof(ipmqindex_t))))
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typedef struct ipm_queue {
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ipm_desc_t ipm_desc[NIPMDESC];
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volatile ipmqindex_t ix_write; /* writer increments and inserts here */
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volatile ipmqindex_t ix_read; /* reader extracts here and increments */
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uint8_t pad[IPMQPADSZ];
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} ipm_queue_t;
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static inline ipmqindex_t
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ipmqnext(ipmqindex_t ix)
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{
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if (++ix >= NIPMDESC)
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ix = 0;
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return ix;
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}
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static inline bool
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ipmqisempty(ipmqindex_t ixr, ipmqindex_t ixw)
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{
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if (ixr == ixw)
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return TRUE;
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return FALSE;
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}
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static inline bool
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ipmqisfull(ipmqindex_t ixr, ipmqindex_t ixw)
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{
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if (ipmqnext(ixw) == ixr)
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return TRUE;
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return FALSE;
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}
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#endif /* _GEMINI_IPMVAR_H_ */
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