298 lines
12 KiB
C
298 lines
12 KiB
C
/* *********************************************************************
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* SB1250 Board Support Package
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*
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* PCI constants File: sb1250_pci.h
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*
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* This module contains constants and macros to describe
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* the PCI interface on the SB1250.
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*
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* SB1250 specification level: User's manual 1/02/02
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*
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* Author: Mitch Lichtenberg (mpl@broadcom.com)
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*
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*********************************************************************
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*
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* Copyright 2000,2001
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* Broadcom Corporation. All rights reserved.
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*
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* This software is furnished under license and may be used and
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* copied only in accordance with the following terms and
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* conditions. Subject to these conditions, you may download,
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* copy, install, use, modify and distribute modified or unmodified
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* copies of this software in source and/or binary form. No title
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* or ownership is transferred hereby.
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*
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* 1) Any source code used, modified or distributed must reproduce
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* and retain this copyright notice and list of conditions as
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* they appear in the source file.
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*
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* 2) No right is granted to use any trade name, trademark, or
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* logo of Broadcom Corporation. Neither the "Broadcom
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* Corporation" name nor any trademark or logo of Broadcom
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* Corporation may be used to endorse or promote products
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* derived from this software without the prior written
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* permission of Broadcom Corporation.
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*
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* 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED
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* WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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* PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT
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* SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN
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* PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
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* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
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* TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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********************************************************************* */
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#ifndef _SB1250_PCI_H
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#define _SB1250_PCI_H
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#include "sb1250_defs.h"
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#define K_PCI_VENDOR_SIBYTE 0x166D
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#define K_PCI_DEVICE_SB1250 0x0001
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/*
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* PCI Interface Type 0 configuration header
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*/
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#define R_PCI_TYPE0_DEVICEID 0x0000
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#define R_PCI_TYPE0_CMDSTATUS 0x0004
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#define R_PCI_TYPE0_CLASSREV 0x0008
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#define R_PCI_TYPE0_DEVHDR 0x000C
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#define R_PCI_TYPE0_BAR0 0x0010 /* translated via mapping table */
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#define R_PCI_TYPE0_BAR1 0x0014 /* reserved */
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#define R_PCI_TYPE0_BAR2 0x0018 /* mbox 0 */
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#define R_PCI_TYPE0_BAR3 0x001C /* mbox 1 */
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#define R_PCI_TYPE0_BAR4 0x0020 /* low memory */
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#define R_PCI_TYPE0_BAR5 0x0024 /* high memory */
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#define R_PCI_TYPE0_CARDBUSCIS 0x0028
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#define R_PCI_TYPE0_SUBSYSID 0x002C
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#define R_PCI_TYPE0_ROMBASE 0x0030
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#define R_PCI_TYPE0_CAPPTR 0x0034 /* not used */
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#define R_PCI_TYPE0_RESERVED1 0x0038
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#define R_PCI_TYPE0_INTGRANT 0x003C /* interrupt pin and grant latency */
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#define R_PCI_TYPE0_TIMEOUT 0x0040 /* FControl, Timeout */
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#define R_PCI_TYPE0_FCONTROL 0x0040 /* FControl, Timeout */
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#define R_PCI_TYPE0_MAPBASE 0x0044 /* 0x44 through 0x80 - map table */
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#define PCI_TYPE0_MAPENTRIES 32 /* 64 bytes, 32 entries */
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#define R_PCI_TYPE0_ERRORADDR 0x0084
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#define R_PCI_TYPE0_ADDSTATUS 0x0088
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#define R_PCI_TYPE0_SUBSYSSET 0x008C /* only accessible from ZBBus */
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#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
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#define R_PCI_TYPE0_READHOST 0x0094 /* Read Host register */
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#define R_PCI_TYPE0_ADXTEND 0x0098 /* Adaptive Extend register */
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#endif /* 1250 PASS2 || 112x PASS1 */
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/*
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* PCI Device ID register
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*/
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#define S_PCI_DEVICEID_VENDOR 0
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#define M_PCI_DEVICEID_VENDOR _SB_MAKEMASK_32(16,S_PCI_DEVICEID_VENDOR)
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#define V_PCI_DEVICEID_VENDOR(x) _SB_MAKEVALUE_32(x,S_PCI_DEVICEID_VENDOR)
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#define G_PCI_DEVICEID_VENDOR(x) _SB_GETVALUE_32(x,S_PCI_DEVICEID_VENDOR,M_PCI_DEVICEID_VENDOR)
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#define S_PCI_DEVICEID_DEVICEID 16
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#define M_PCI_DEVICEID_DEVICEID _SB_MAKEMASK_32(16,S_PCI_DEVICEID_DEVICEID)
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#define V_PCI_DEVICEID_DEVICEID(x) _SB_MAKEVALUE_32(x,S_PCI_DEVICEID_DEVICEID)
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#define G_PCI_DEVICEID_DEVICEID(x) _SB_GETVALUE_32(x,S_PCI_DEVICEID_DEVICEID,M_PCI_DEVICEID_DEVICEID)
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/*
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* PCI Command Register (Table 8-4)
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*/
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#define M_PCI_CMD_IOSPACE_EN _SB_MAKEMASK1_32(0)
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#define M_PCI_CMD_MEMSPACE_EN _SB_MAKEMASK1_32(1)
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#define M_PCI_CMD_MASTER_EN _SB_MAKEMASK1_32(2)
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#define M_PCI_CMD_SPECCYC_EN _SB_MAKEMASK1_32(3)
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#define M_PCI_CMD_MEMWRINV_EN _SB_MAKEMASK1_32(4)
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#define M_PCI_CMD_VGAPALSNP_EN _SB_MAKEMASK1_32(5)
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#define M_PCI_CMD_PARERRRESP _SB_MAKEMASK1_32(6)
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#define M_PCI_CMD_STEPCTRL _SB_MAKEMASK1_32(7)
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#define M_PCI_CMD_SERR_EN _SB_MAKEMASK1_32(8)
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#define M_PCI_CMD_FASTB2B_EN _SB_MAKEMASK1_32(9)
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/*
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* PCI class and revision registers
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*/
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#define S_PCI_CLASSREV_REV 0
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#define M_PCI_CLASSREV_REV _SB_MAKEMASK_32(8,S_PCI_CLASSREV_REV)
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#define V_PCI_CLASSREV_REV(x) _SB_MAKEVALUE_32(x,S_PCI_CLASSREV_REV)
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#define G_PCI_CLASSREV_REV(x) _SB_GETVALUE_32(x,S_PCI_CLASSREV_REV,M_PCI_CLASSREV_REV)
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#define S_PCI_CLASSREV_CLASS 8
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#define M_PCI_CLASSREV_CLASS _SB_MAKEMASK_32(24,S_PCI_CLASSREV_CLASS)
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#define V_PCI_CLASSREV_CLASS(x) _SB_MAKEVALUE_32(x,S_PCI_CLASSREV_CLASS)
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#define G_PCI_CLASSREV_CLASS(x) _SB_GETVALUE_32(x,S_PCI_CLASSREV_CLASS,M_PCI_CLASSREV_CLASS)
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#define K_PCI_REV 0x01
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#define K_PCI_CLASS 0x060000
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/*
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* Device Header (offset 0x0C)
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*/
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#define S_PCI_DEVHDR_CLINESZ 0
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#define M_PCI_DEVHDR_CLINESZ _SB_MAKEMASK_32(8,S_PCI_DEVHDR_CLINESZ)
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#define V_PCI_DEVHDR_CLINESZ(x) _SB_MAKEVALUE_32(x,S_PCI_DEVHDR_CLINESZ)
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#define G_PCI_DEVHDR_CLINESZ(x) _SB_GETVALUE_32(x,S_PCI_DEVHDR_CLINESZ,M_PCI_DEVHDR_CLINESZ)
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#define S_PCI_DEVHDR_LATTMR 8
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#define M_PCI_DEVHDR_LATTMR _SB_MAKEMASK_32(8,S_PCI_DEVHDR_LATTMR)
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#define V_PCI_DEVHDR_LATTMR(x) _SB_MAKEVALUE_32(x,S_PCI_DEVHDR_LATTMR)
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#define G_PCI_DEVHDR_LATTMR(x) _SB_GETVALUE_32(x,S_PCI_DEVHDR_LATTMR,M_PCI_DEVHDR_LATTMR)
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#define S_PCI_DEVHDR_HDRTYPE 16
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#define M_PCI_DEVHDR_HDRTYPE _SB_MAKEMASK_32(8,S_PCI_DEVHDR_HDRTYPE)
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#define V_PCI_DEVHDR_HDRTYPE(x) _SB_MAKEVALUE_32(x,S_PCI_DEVHDR_HDRTYPE)
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#define G_PCI_DEVHDR_HDRTYPE(x) _SB_GETVALUE_32(x,S_PCI_DEVHDR_HDRTYPE,M_PCI_DEVHDR_HDRTYPE)
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#define K_PCI_DEVHDR_HDRTYPE_TYPE0 0
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#define S_PCI_DEVHDR_BIST 24
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#define M_PCI_DEVHDR_BIST _SB_MAKEMASK_32(8,S_PCI_DEVHDR_BIST)
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#define V_PCI_DEVHDR_BIST(x) _SB_MAKEVALUE_32(x,S_PCI_DEVHDR_BIST)
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#define G_PCI_DEVHDR_BIST(x) _SB_GETVALUE_32(x,S_PCI_DEVHDR_BIST,M_PCI_DEVHDR_BIST)
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/*
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* PCI Status Register (Table 8-5). Note that these constants
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* assume you've read the command and status register
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* together (32-bit read at offset 0x04)
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*/
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#define M_PCI_STATUS_CAPLIST _SB_MAKEMASK1_32(20)
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#define M_PCI_STATUS_66MHZCAP _SB_MAKEMASK1_32(21)
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#define M_PCI_STATUS_RESERVED2 _SB_MAKEMASK1_32(22)
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#define M_PCI_STATUS_FASTB2BCAP _SB_MAKEMASK1_32(23)
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#define M_PCI_STATUS_MSTRDPARERR _SB_MAKEMASK1_32(24)
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#define S_PCI_STATUS_DEVSELTIMING 25
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#define M_PCI_STATUS_DEVSELTIMING _SB_MAKEMASK_32(2,S_PCI_STATUS_DEVSELTIMING)
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#define V_PCI_STATUS_DEVSELTIMING(x) _SB_MAKEVALUE_32(x,S_PCI_STATUS_DEVSELTIMING)
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#define G_PCI_STATUS_DEVSELTIMING(x) _SB_GETVALUE_32(x,S_PCI_STATUS_DEVSELTIMING,M_PCI_STATUS_DEVSELTIMING)
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#define M_PCI_STATUS_SIGDTGTABORT _SB_MAKEMASK1_32(27)
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#define M_PCI_STATUS_RCVDTGTABORT _SB_MAKEMASK1_32(28)
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#define M_PCI_STATUS_RCVDMSTRABORT _SB_MAKEMASK1_32(29)
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#define M_PCI_STATUS_SIGDSERR _SB_MAKEMASK1_32(30)
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#define M_PCI_STATUS_DETPARERR _SB_MAKEMASK1_32(31)
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/*
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* Device Header Register (Table 8-6, Table 8-7)
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*/
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#define S_PCI_DEVHDR_CLINESZ 0
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#define M_PCI_DEVHDR_CLINESZ _SB_MAKEMASK_32(8,S_PCI_DEVHDR_CLINESZ)
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#define V_PCI_DEVHDR_CLINESZ(x) _SB_MAKEVALUE_32(x,S_PCI_DEVHDR_CLINESZ)
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#define G_PCI_DEVHDR_CLINESZ(x) _SB_GETVALUE_32(x,S_PCI_DEVHDR_CLINESZ,M_PCI_DEVHDR_CLINESZ)
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#define S_PCI_DEVHDR_LATTIME 8
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#define M_PCI_DEVHDR_LATTIME _SB_MAKEMASK_32(8,S_PCI_DEVHDR_LATTIME)
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#define V_PCI_DEVHDR_LATTIME(x) _SB_MAKEVALUE_32(x,S_PCI_DEVHDR_LATTIME)
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#define G_PCI_DEVHDR_LATTIME(x) _SB_GETVALUE_32(x,S_PCI_DEVHDR_LATTIME,M_PCI_DEVHDR_LATTIME)
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#define S_PCI_DEVHDR_HDRTYPE 16
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#define M_PCI_DEVHDR_HDRTYPE _SB_MAKEMASK_32(8,S_PCI_DEVHDR_HDRTYPE)
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#define V_PCI_DEVHDR_HDRTYPE(x) _SB_MAKEVALUE_32(x,S_PCI_DEVHDR_HDRTYPE)
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#define G_PCI_DEVHDR_HDRTYPE(x) _SB_GETVALUE_32(x,S_PCI_DEVHDR_HDRTYPE,M_PCI_DEVHDR_HDRTYPE)
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#define S_PCI_DEVHDR_BIST 24
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#define M_PCI_DEVHDR_BIST _SB_MAKEMASK_32(8,S_PCI_DEVHDR_BIST)
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#define V_PCI_DEVHDR_BIST(x) _SB_MAKEVALUE_32(x,S_PCI_DEVHDR_BIST)
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#define G_PCI_DEVHDR_BIST(x) _SB_GETVALUE_32(x,S_PCI_DEVHDR_BIST,M_PCI_DEVHDR_BIST)
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/*
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* Timeout and feature control Register (Table 8-8) (Table 8-9)
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* Note that these constants assume you've read the timeout/fcontrol register
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* together (32-bit read at offset 0x40)
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*/
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#define S_PCI_TIMEOUT_TRDY 0
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#define M_PCI_TIMEOUT_TRDY _SB_MAKEMASK_32(8,S_PCI_TIMEOUT_TRDY)
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#define V_PCI_TIMEOUT_TRDY(x) _SB_MAKEVALUE_32(x,S_PCI_TIMEOUT_TRDY)
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#define G_PCI_TIMEOUT_TRDY(x) _SB_GETVALUE_32(x,S_PCI_TIMEOUT_TRDY,M_PCI_TIMEOUT_TRDY)
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#define S_PCI_TIMEOUT_RETRY 8
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#define M_PCI_TIMEOUT_RETRY _SB_MAKEMASK_32(8,S_PCI_TIMEOUT_RETRY)
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#define V_PCI_TIMEOUT_RETRY(x) _SB_MAKEVALUE_32(x,S_PCI_TIMEOUT_RETRY)
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#define G_PCI_TIMEOUT_RETRY(x) _SB_GETVALUE_32(x,S_PCI_TIMEOUT_RETRY,M_PCI_TIMEOUT_RETRY)
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#define M_PCI_FCONTROL_BAR4_EN _SB_MAKEMASK1_32(16)
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#define M_PCI_FCONTROL_BAR5_EN _SB_MAKEMASK1_32(17)
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#define M_PCI_FCONTROL_PTP_EN _SB_MAKEMASK1_32(18)
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#define M_PCI_FCONTROL_ADAPT_RETRY_EN _SB_MAKEMASK1_32(19)
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#define S_PCI_FCONTROL_MIN_TAR_RETRY 20
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#define M_PCI_FCONTROL_MIN_TAR_RETRY _SB_MAKEMASK_32(3,S_PCI_FCONTROL_MIN_TAR_RETRY)
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#define V_PCI_FCONTROL_MIN_TAR_RETRY(x) _SB_MAKEVALUE_32(x,S_PCI_FCONTROL_MIN_TAR_RETRY)
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#define G_PCI_FCONTROL_MIN_TAR_RETRY(x) _SB_GETVALUE_32(x,S_PCI_FCONTROL_MIN_TAR_RETRY,M_PCI_FCONTROL_MIN_TAR_RETRY)
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#define S_PCI_FCONTROL_NOM_TAR_RETRY 23
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#define M_PCI_FCONTROL_NOM_TAR_RETRY _SB_MAKEMASK_32(4,S_PCI_FCONTROL_NOM_TAR_RETRY)
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#define V_PCI_FCONTROL_NOM_TAR_RETRY(x) _SB_MAKEVALUE_32(x,S_PCI_FCONTROL_NOM_TAR_RETRY)
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#define G_PCI_FCONTROL_NOM_TAR_RETRY(x) _SB_GETVALUE_32(x,S_PCI_FCONTROL_NOM_TAR_RETRY,M_PCI_FCONTROL_NOM_TAR_RETRY)
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#define S_PCI_FCONTROL_MAX_TAR_RETRY 27
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#define M_PCI_FCONTROL_MAX_TAR_RETRY _SB_MAKEMASK_32(5,S_PCI_FCONTROL_MAX_TAR_RETRY)
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#define V_PCI_FCONTROL_MAX_TAR_RETRY(x) _SB_MAKEVALUE_32(x,S_PCI_FCONTROL_MAX_TAR_RETRY)
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#define G_PCI_FCONTROL_MAX_TAR_RETRY(x) _SB_GETVALUE_32(x,S_PCI_FCONTROL_MAX_TAR_RETRY,M_PCI_FCONTROL_MAX_TAR_RETRY)
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/*
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* BAR0 Map Table Entry (Offsets 0x40-0x80) (Table 8-10)
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*/
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#define M_PCI_BAR0MAP_ENABLE _SB_MAKEMASK1_32(0)
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#define M_PCI_BAR0MAP_SENDLDT _SB_MAKEMASK1_32(1)
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#define S_PCI_BAR0MAP_ADDR 12
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#define M_PCI_BAR0MAP_ADDR _SB_MAKEMASK_32(20,S_PCI_BAR0MAP_ADDR)
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/*
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* Additional Status Register (Table 8-11)
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*/
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#define M_PCI_ASTATUS_HOTPLUG_EN _SB_MAKEMASK1_32(0)
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#define M_PCI_ASTATUS_SERR_DET _SB_MAKEMASK1_32(1)
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#define M_PCI_ASTATUS_TRDYERR _SB_MAKEMASK1_32(2)
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#define M_PCI_ASTATUS_RETRTYERR _SB_MAKEMASK1_32(3)
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#define M_PCI_ASTATUS_TRDYINTMASK _SB_MAKEMASK1_32(4)
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#define M_PCI_ASTATUS_RETRYINTMASK _SB_MAKEMASK1_32(5)
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#define M_PCI_ASTATUS_SIGNALINTA _SB_MAKEMASK1_32(6)
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#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
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/*
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* Read Host Register
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*/
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#define M_PCI_READHOST_RDHOST _SB_MAKEMASK1_32(0)
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/*
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* Adaptive Extend Register
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*/
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#define S_PCI_ADXTEND_NOM_TAR_RETRY 1
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#define M_PCI_ADXTEND_NOM_TAR_RETRY _SB_MAKEMASK_32(3,S_PCI_ADXTEND_NOM_TAR_RETRY)
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#define V_PCI_ADXTEND_NOM_TAR_RETRY(x) _SB_MAKEVALUE_32(x,S_PCI_ADXTEND_NOM_TAR_RETRY)
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#define G_PCI_ADXTEND_NOM_TAR_RETRY(x) _SB_GETVALUE_32(x,S_PCI_ADXTEND_NOM_TAR_RETRY,M_PCI_ADXTEND_NOM_TAR_RETRY)
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#define S_PCI_ADXTEND_MAX_TAR_RETRY 4
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#define M_PCI_ADXTEND_MAX_TAR_RETRY _SB_MAKEMASK_32(2,S_PCI_ADXTEND_MAX_TAR_RETRY)
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#define V_PCI_ADXTEND_MAX_TAR_RETRY(x) _SB_MAKEVALUE_32(x,S_PCI_ADXTEND_MAX_TAR_RETRY)
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#define G_PCI_ADXTEND_MAX_TAR_RETRY(x) _SB_GETVALUE_32(x,S_PCI_ADXTEND_MAX_TAR_RETRY,M_PCI_ADXTEND_MAX_TAR_RETRY)
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#define M_PCI_ADXTEND_DIS_DMAR_IOW_DEP _SB_MAKEMASK1_32(6)
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#define M_PCI_ADXTEND_DIS_MEMRD_BE _SB_MAKEMASK1_32(6)
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#endif /* 1250 PASS2 || 112x PASS1 */
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#endif
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