265 lines
12 KiB
C
265 lines
12 KiB
C
/* *********************************************************************
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* SB1250 Board Support Package
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*
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* Interrupt Mapper definitions File: sb1250_int.h
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*
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* This module contains constants for manipulating the SB1250's
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* interrupt mapper and definitions for the interrupt sources.
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*
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* SB1250 specification level: User's manual 1/02/02
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*
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* Author: Mitch Lichtenberg (mpl@broadcom.com)
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*
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*********************************************************************
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*
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* Copyright 2000,2001
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* Broadcom Corporation. All rights reserved.
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*
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* This software is furnished under license and may be used and
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* copied only in accordance with the following terms and
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* conditions. Subject to these conditions, you may download,
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* copy, install, use, modify and distribute modified or unmodified
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* copies of this software in source and/or binary form. No title
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* or ownership is transferred hereby.
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*
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* 1) Any source code used, modified or distributed must reproduce
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* and retain this copyright notice and list of conditions as
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* they appear in the source file.
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*
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* 2) No right is granted to use any trade name, trademark, or
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* logo of Broadcom Corporation. Neither the "Broadcom
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* Corporation" name nor any trademark or logo of Broadcom
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* Corporation may be used to endorse or promote products
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* derived from this software without the prior written
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* permission of Broadcom Corporation.
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*
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* 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED
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* WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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* PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT
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* SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN
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* PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
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* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
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* TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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********************************************************************* */
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#ifndef _SB1250_INT_H
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#define _SB1250_INT_H
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#include "sb1250_defs.h"
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/* *********************************************************************
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* Interrupt Mapper Constants
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********************************************************************* */
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/*
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* Interrupt sources (Table 4-8, UM 0.2)
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*
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* First, the interrupt numbers.
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*/
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#define K_INT_WATCHDOG_TIMER_0 0
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#define K_INT_WATCHDOG_TIMER_1 1
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#define K_INT_TIMER_0 2
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#define K_INT_TIMER_1 3
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#define K_INT_TIMER_2 4
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#define K_INT_TIMER_3 5
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#define K_INT_SMB_0 6
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#define K_INT_SMB_1 7
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#define K_INT_UART_0 8
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#define K_INT_UART_1 9
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#define K_INT_SER_0 10
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#define K_INT_SER_1 11
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#define K_INT_PCMCIA 12
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#define K_INT_ADDR_TRAP 13
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#define K_INT_PERF_CNT 14
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#define K_INT_TRACE_FREEZE 15
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#define K_INT_BAD_ECC 16
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#define K_INT_COR_ECC 17
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#define K_INT_IO_BUS 18
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#define K_INT_MAC_0 19
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#define K_INT_MAC_1 20
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#define K_INT_MAC_2 21
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#define K_INT_DM_CH_0 22
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#define K_INT_DM_CH_1 23
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#define K_INT_DM_CH_2 24
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#define K_INT_DM_CH_3 25
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#define K_INT_MBOX_0 26
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#define K_INT_MBOX_1 27
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#define K_INT_MBOX_2 28
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#define K_INT_MBOX_3 29
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#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
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#define K_INT_CYCLE_CP0_INT 30
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#define K_INT_CYCLE_CP1_INT 31
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#endif /* 1250 PASS2 || 112x PASS1 */
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#define K_INT_GPIO_0 32
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#define K_INT_GPIO_1 33
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#define K_INT_GPIO_2 34
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#define K_INT_GPIO_3 35
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#define K_INT_GPIO_4 36
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#define K_INT_GPIO_5 37
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#define K_INT_GPIO_6 38
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#define K_INT_GPIO_7 39
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#define K_INT_GPIO_8 40
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#define K_INT_GPIO_9 41
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#define K_INT_GPIO_10 42
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#define K_INT_GPIO_11 43
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#define K_INT_GPIO_12 44
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#define K_INT_GPIO_13 45
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#define K_INT_GPIO_14 46
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#define K_INT_GPIO_15 47
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#define K_INT_LDT_FATAL 48
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#define K_INT_LDT_NONFATAL 49
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#define K_INT_LDT_SMI 50
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#define K_INT_LDT_NMI 51
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#define K_INT_LDT_INIT 52
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#define K_INT_LDT_STARTUP 53
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#define K_INT_LDT_EXT 54
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#define K_INT_PCI_ERROR 55
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#define K_INT_PCI_INTA 56
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#define K_INT_PCI_INTB 57
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#define K_INT_PCI_INTC 58
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#define K_INT_PCI_INTD 59
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#define K_INT_SPARE_2 60
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#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
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#define K_INT_MAC_0_CH1 61
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#define K_INT_MAC_1_CH1 62
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#define K_INT_MAC_2_CH1 63
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#endif /* 1250 PASS2 || 112x PASS1 */
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/*
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* Mask values for each interrupt
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*/
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#define M_INT_WATCHDOG_TIMER_0 _SB_MAKEMASK1(K_INT_WATCHDOG_TIMER_0)
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#define M_INT_WATCHDOG_TIMER_1 _SB_MAKEMASK1(K_INT_WATCHDOG_TIMER_1)
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#define M_INT_TIMER_0 _SB_MAKEMASK1(K_INT_TIMER_0)
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#define M_INT_TIMER_1 _SB_MAKEMASK1(K_INT_TIMER_1)
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#define M_INT_TIMER_2 _SB_MAKEMASK1(K_INT_TIMER_2)
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#define M_INT_TIMER_3 _SB_MAKEMASK1(K_INT_TIMER_3)
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#define M_INT_SMB_0 _SB_MAKEMASK1(K_INT_SMB_0)
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#define M_INT_SMB_1 _SB_MAKEMASK1(K_INT_SMB_1)
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#define M_INT_UART_0 _SB_MAKEMASK1(K_INT_UART_0)
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#define M_INT_UART_1 _SB_MAKEMASK1(K_INT_UART_1)
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#define M_INT_SER_0 _SB_MAKEMASK1(K_INT_SER_0)
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#define M_INT_SER_1 _SB_MAKEMASK1(K_INT_SER_1)
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#define M_INT_PCMCIA _SB_MAKEMASK1(K_INT_PCMCIA)
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#define M_INT_ADDR_TRAP _SB_MAKEMASK1(K_INT_ADDR_TRAP)
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#define M_INT_PERF_CNT _SB_MAKEMASK1(K_INT_PERF_CNT)
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#define M_INT_TRACE_FREEZE _SB_MAKEMASK1(K_INT_TRACE_FREEZE)
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#define M_INT_BAD_ECC _SB_MAKEMASK1(K_INT_BAD_ECC)
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#define M_INT_COR_ECC _SB_MAKEMASK1(K_INT_COR_ECC)
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#define M_INT_IO_BUS _SB_MAKEMASK1(K_INT_IO_BUS)
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#define M_INT_MAC_0 _SB_MAKEMASK1(K_INT_MAC_0)
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#define M_INT_MAC_1 _SB_MAKEMASK1(K_INT_MAC_1)
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#define M_INT_MAC_2 _SB_MAKEMASK1(K_INT_MAC_2)
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#define M_INT_DM_CH_0 _SB_MAKEMASK1(K_INT_DM_CH_0)
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#define M_INT_DM_CH_1 _SB_MAKEMASK1(K_INT_DM_CH_1)
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#define M_INT_DM_CH_2 _SB_MAKEMASK1(K_INT_DM_CH_2)
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#define M_INT_DM_CH_3 _SB_MAKEMASK1(K_INT_DM_CH_3)
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#define M_INT_MBOX_0 _SB_MAKEMASK1(K_INT_MBOX_0)
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#define M_INT_MBOX_1 _SB_MAKEMASK1(K_INT_MBOX_1)
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#define M_INT_MBOX_2 _SB_MAKEMASK1(K_INT_MBOX_2)
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#define M_INT_MBOX_3 _SB_MAKEMASK1(K_INT_MBOX_3)
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#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
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#define M_INT_CYCLE_CP0_INT _SB_MAKEMASK1(K_INT_CYCLE_CP0_INT)
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#define M_INT_CYCLE_CP1_INT _SB_MAKEMASK1(K_INT_CYCLE_CP1_INT)
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#endif /* 1250 PASS2 || 112x PASS1 */
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#define M_INT_GPIO_0 _SB_MAKEMASK1(K_INT_GPIO_0)
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#define M_INT_GPIO_1 _SB_MAKEMASK1(K_INT_GPIO_1)
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#define M_INT_GPIO_2 _SB_MAKEMASK1(K_INT_GPIO_2)
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#define M_INT_GPIO_3 _SB_MAKEMASK1(K_INT_GPIO_3)
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#define M_INT_GPIO_4 _SB_MAKEMASK1(K_INT_GPIO_4)
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#define M_INT_GPIO_5 _SB_MAKEMASK1(K_INT_GPIO_5)
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#define M_INT_GPIO_6 _SB_MAKEMASK1(K_INT_GPIO_6)
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#define M_INT_GPIO_7 _SB_MAKEMASK1(K_INT_GPIO_7)
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#define M_INT_GPIO_8 _SB_MAKEMASK1(K_INT_GPIO_8)
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#define M_INT_GPIO_9 _SB_MAKEMASK1(K_INT_GPIO_9)
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#define M_INT_GPIO_10 _SB_MAKEMASK1(K_INT_GPIO_10)
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#define M_INT_GPIO_11 _SB_MAKEMASK1(K_INT_GPIO_11)
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#define M_INT_GPIO_12 _SB_MAKEMASK1(K_INT_GPIO_12)
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#define M_INT_GPIO_13 _SB_MAKEMASK1(K_INT_GPIO_13)
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#define M_INT_GPIO_14 _SB_MAKEMASK1(K_INT_GPIO_14)
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#define M_INT_GPIO_15 _SB_MAKEMASK1(K_INT_GPIO_15)
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#define M_INT_LDT_FATAL _SB_MAKEMASK1(K_INT_LDT_FATAL)
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#define M_INT_LDT_NONFATAL _SB_MAKEMASK1(K_INT_LDT_NONFATAL)
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#define M_INT_LDT_SMI _SB_MAKEMASK1(K_INT_LDT_SMI)
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#define M_INT_LDT_NMI _SB_MAKEMASK1(K_INT_LDT_NMI)
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#define M_INT_LDT_INIT _SB_MAKEMASK1(K_INT_LDT_INIT)
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#define M_INT_LDT_STARTUP _SB_MAKEMASK1(K_INT_LDT_STARTUP)
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#define M_INT_LDT_EXT _SB_MAKEMASK1(K_INT_LDT_EXT)
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#define M_INT_PCI_ERROR _SB_MAKEMASK1(K_INT_PCI_ERROR)
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#define M_INT_PCI_INTA _SB_MAKEMASK1(K_INT_PCI_INTA)
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#define M_INT_PCI_INTB _SB_MAKEMASK1(K_INT_PCI_INTB)
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#define M_INT_PCI_INTC _SB_MAKEMASK1(K_INT_PCI_INTC)
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#define M_INT_PCI_INTD _SB_MAKEMASK1(K_INT_PCI_INTD)
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#define M_INT_SPARE_2 _SB_MAKEMASK1(K_INT_SPARE_2)
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#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
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#define M_INT_MAC_0_CH1 _SB_MAKEMASK1(K_INT_MAC_0_CH1)
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#define M_INT_MAC_1_CH1 _SB_MAKEMASK1(K_INT_MAC_1_CH1)
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#define M_INT_MAC_2_CH1 _SB_MAKEMASK1(K_INT_MAC_2_CH1)
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#endif /* 1250 PASS2 || 112x PASS1 */
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/*
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* Interrupt mappings
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*/
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#define K_INT_MAP_I0 0 /* interrupt pins on processor */
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#define K_INT_MAP_I1 1
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#define K_INT_MAP_I2 2
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#define K_INT_MAP_I3 3
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#define K_INT_MAP_I4 4
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#define K_INT_MAP_I5 5
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#define K_INT_MAP_NMI 6 /* nonmaskable */
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#define K_INT_MAP_DINT 7 /* debug interrupt */
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/*
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* LDT Interrupt Set Register (table 4-5)
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*/
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#define S_INT_LDT_INTMSG 0
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#define M_INT_LDT_INTMSG _SB_MAKEMASK(3,S_INT_LDT_INTMSG)
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#define V_INT_LDT_INTMSG(x) _SB_MAKEVALUE(x,S_INT_LDT_INTMSG)
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#define G_INT_LDT_INTMSG(x) _SB_GETVALUE(x,S_INT_LDT_INTMSG,M_INT_LDT_INTMSG)
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#define K_INT_LDT_INTMSG_FIXED 0
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#define K_INT_LDT_INTMSG_ARBITRATED 1
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#define K_INT_LDT_INTMSG_SMI 2
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#define K_INT_LDT_INTMSG_NMI 3
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#define K_INT_LDT_INTMSG_INIT 4
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#define K_INT_LDT_INTMSG_STARTUP 5
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#define K_INT_LDT_INTMSG_EXTINT 6
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#define K_INT_LDT_INTMSG_RESERVED 7
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#define M_INT_LDT_EDGETRIGGER 0
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#define M_INT_LDT_LEVELTRIGGER _SB_MAKEMASK1(3)
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#define M_INT_LDT_PHYSICALDEST 0
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#define M_INT_LDT_LOGICALDEST _SB_MAKEMASK1(4)
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#define S_INT_LDT_INTDEST 5
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#define M_INT_LDT_INTDEST _SB_MAKEMASK(10,S_INT_LDT_INTDEST)
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#define V_INT_LDT_INTDEST(x) _SB_MAKEVALUE(x,S_INT_LDT_INTDEST)
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#define G_INT_LDT_INTDEST(x) _SB_GETVALUE(x,S_INT_LDT_INTDEST,M_INT_LDT_INTDEST)
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#define S_INT_LDT_VECTOR 13
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#define M_INT_LDT_VECTOR _SB_MAKEMASK(8,S_INT_LDT_VECTOR)
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#define V_INT_LDT_VECTOR(x) _SB_MAKEVALUE(x,S_INT_LDT_VECTOR)
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#define G_INT_LDT_VECTOR(x) _SB_GETVALUE(x,S_INT_LDT_VECTOR,M_INT_LDT_VECTOR)
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/*
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* Vector format (Table 4-6)
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*/
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#define M_LDTVECT_RAISEINT 0x00
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#define M_LDTVECT_RAISEMBOX 0x40
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#endif
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