8bcac06284
MACHINE_NEW_NONCONTIG interface implementation, which is now enabled on all systems. Thanks to Jason Thorpe for his work on the hp300 port, from which most of the code used here was derived. XXX In spite of the fact that it works on the hp300, UVM does not (yet) work well under load on mac68k.
109 lines
4.5 KiB
C
109 lines
4.5 KiB
C
/* $NetBSD: psc.h,v 1.3 1998/04/24 05:27:24 scottr Exp $ */
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/*-
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* Copyright (c) 1997 David Huang <khym@bga.com>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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/*
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* Some register definitions for the PSC, present only on the
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* Centris/Quadra 660av and the Quadra 840av.
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*/
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extern volatile u_int8_t *PSCBase;
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#define psc_reg1(r) (*((volatile u_int8_t *)(PSCBase+r)))
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#define psc_reg2(r) (*((volatile u_int16_t *)(PSCBase+r)))
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#define psc_reg4(r) (*((volatile u_int32_t *)(PSCBase+r)))
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void psc_init __P((void));
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int add_psc_lev3_intr __P((void (*)(void *), void *));
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int add_psc_lev4_intr __P((int, int (*)(void *), void *));
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int add_psc_lev5_intr __P((int, void (*)(void *), void *));
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int add_psc_lev6_intr __P((int, void (*)(void *), void *));
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int remove_psc_lev3_intr __P((void));
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int remove_psc_lev4_intr __P((int));
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int remove_psc_lev5_intr __P((int));
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int remove_psc_lev6_intr __P((int));
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/*
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* Reading an interrupt status register returns a mask of the
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* currently interrupting devices (one bit per device). Reading an
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* interrupt enable register returns a mask of the currently enabled
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* devices. Writing an interrupt enable register with the MSB set
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* enables the interrupts in the lower 4 bits, while writing with the
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* MSB clear disables the corresponding interrupts.
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* e.g. write 0x81 to enable device 0, write 0x86 to enable devices 1
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* and 2, write 0x02 to disable device 1.
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*
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* Level 3 device 0 is MACE
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* Level 4 device 0 is 3210 DSP?
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* Level 4 device 1 is SCC channel A (modem port)
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* Level 4 device 2 is SCC channel B (printer port)
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* Level 4 device 3 is MACE DMA completion
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* Level 5 device 0 is 3210 DSP?
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* Level 5 device 1 is 3210 DSP?
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* Level 6 device 0 is ?
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* Level 6 device 1 is ?
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* Level 6 device 2 is ?
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*/
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/* PSC interrupt registers */
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#define PSC_LEV3_ISR 0x130 /* level 3 interrupt status register */
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#define PSC_LEV3_IER 0x134 /* level 3 interrupt enable register */
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#define PSCINTR_ENET 0 /* Ethernet interrupt */
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#define PSC_LEV4_ISR 0x140 /* level 4 interrupt status register */
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#define PSC_LEV4_IER 0x144 /* level 4 interrupt enable register */
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#define PSCINTR_SCCA 1 /* SCC channel A interrupt */
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#define PSCINTR_SCCB 2 /* SCC channel B interrupt */
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#define PSCINTR_ENET_DMA 3 /* Ethernet DMA completion interrupt */
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#define PSC_LEV5_ISR 0x150 /* level 5 interrupt status register */
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#define PSC_LEV5_IER 0x154 /* level 5 interrupt enable register */
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#define PSC_LEV6_ISR 0x160 /* level 6 interrupt status register */
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#define PSC_LEV6_IER 0x164 /* level 6 interrupt enable register */
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/* PSC DMA channel control registers */
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#define PSC_ENETRD_CTL 0xc10 /* MACE receive DMA channel control/status */
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#define PSC_ENETWR_CTL 0xc20 /* MACE transmit DMA channel control/status */
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/* PSC DMA channels */
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#define PSC_ENETRD_ADDR 0x1020 /* MACE receive DMA address register */
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#define PSC_ENETRD_LEN 0x1024 /* MACE receive DMA buffer count */
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#define PSC_ENETRD_CMD 0x1028 /* MACE receive DMA command register */
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#define PSC_ENETWR_ADDR 0x1040 /* MACE transmit DMA address register */
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#define PSC_ENETWR_LEN 0x1044 /* MACE transmit DMA length */
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#define PSC_ENETWR_CMD 0x1048 /* MACE transmit DMA command register */
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/*
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* PSC DMA channels are controlled by two sets of registers (see p.29
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* of the Quadra 840av and Centris 660av Developer Note). Add the
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* following offsets to get the desired register set.
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*/
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#define PSC_SET0 0x00
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#define PSC_SET1 0x10
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