thorpej ba9581a345 Reorder the device table to make the UART at J9 attach before the ... UART at J10 (this is the same ordering the RedBoot uses, and also is intuitive).		2001-11-19 19:08:33 +00:00
..
com_obio.c	Rework and fleshing out of Intel IQ80310 XScale eval board support.	2001-11-07 00:33:22 +00:00
i80312_mainbus.c	Add support for PCI DMA on the i80312. We currently just do	2001-11-09 23:15:52 +00:00
iq80310_7seg.c	We were already cheating w/ CPLD register access, so cheat all the	2001-11-07 02:24:18 +00:00
iq80310_intr.c	When we read the interrupt status bits, mask it with the shadow copy	2001-11-07 02:56:18 +00:00
iq80310_irq.S	* Pass the IRQ number to stray_irqhandler() and display it in	2001-11-07 02:06:37 +00:00
iq80310_machdep.c	Allocate the appropriate space for the XScale global cache clean code.	2001-11-11 17:30:14 +00:00
iq80310_pci.c	Fix typos in determing the ATU and PPB bus numbers.	2001-11-09 22:47:48 +00:00
iq80310_timer.c	Fix delay().	2001-11-08 02:12:05 +00:00
iq80310reg.h	* Define fixed virtual addresses for the Primary and Secondary	2001-11-08 03:28:53 +00:00
iq80310var.h	PCI interrupt mapping support for the IQ80310.	2001-11-09 20:58:57 +00:00
obio_space_asm.S	Rework and fleshing out of Intel IQ80310 XScale eval board support.	2001-11-07 00:33:22 +00:00
obio_space.c	Rework and fleshing out of Intel IQ80310 XScale eval board support.	2001-11-07 00:33:22 +00:00
obio.c	Reorder the device table to make the UART at J9 attach before the	2001-11-19 19:08:33 +00:00
obiovar.h	Rework and fleshing out of Intel IQ80310 XScale eval board support.	2001-11-07 00:33:22 +00:00